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1 /*
2 * K2G EVM : Board initialization
3 *
4 * (C) Copyright 2015
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9 #include <common.h>
10 #include <asm/arch/clock.h>
11 #include "mux-k2g.h"
12
13 #define SYS_CLK 24000000
14
15 unsigned int external_clk[ext_clk_count] = {
16 [sys_clk] = SYS_CLK,
17 [pa_clk] = SYS_CLK,
18 [tetris_clk] = SYS_CLK,
19 [ddr3a_clk] = SYS_CLK,
20 [uart_clk] = SYS_CLK,
21 };
22
23 static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4};
24 static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4};
25 static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
26 static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
27 static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
28
29 struct pll_init_data *get_pll_init_data(int pll)
30 {
31 struct pll_init_data *data = NULL;
32
33 switch (pll) {
34 case MAIN_PLL:
35 data = &main_pll_config;
36 break;
37 case TETRIS_PLL:
38 data = &tetris_pll_config;
39 break;
40 case NSS_PLL:
41 data = &nss_pll_config;
42 break;
43 case UART_PLL:
44 data = &uart_pll_config;
45 break;
46 case DDR3_PLL:
47 data = &ddr3_pll_config;
48 break;
49 default:
50 data = NULL;
51 }
52
53 return data;
54 }
55
56 s16 divn_val[16] = {
57 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
58 };
59
60 #ifdef CONFIG_BOARD_EARLY_INIT_F
61 int board_early_init_f(void)
62 {
63 init_plls();
64
65 k2g_mux_config();
66
67 return 0;
68 }
69 #endif
70
71 #ifdef CONFIG_SPL_BUILD
72 void spl_init_keystone_plls(void)
73 {
74 init_plls();
75 }
76 #endif