board/ti/omap1510inn/omap1510innovator.c

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  *
   6  * (C) Copyright 2002
   7  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
   8  *
   9  * (C) Copyright 2003
  10  * Texas Instruments, <www.ti.com>
  11  * Kshitij Gupta <Kshitij@ti.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 #include <common.h>
  33 #include <netdev.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 static void flash__init (void);
  38 static void ether__init (void);
  39
  40 static inline void delay (unsigned long loops)
  41 {
  42         __asm__ volatile ("1:\n"
  43                           "subs %0, %1, #1\n"
  44                           "bne 1b":"=r" (loops):"0" (loops));
  45 }
  46
  47 /*
  48  * Miscellaneous platform dependent initialisations
  49  */
  50
  51 int board_init (void)
  52 {
  53         /* arch number of OMAP 1510-Board */
  54         gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
  55
  56         /* adress of boot parameters */
  57         gd->bd->bi_boot_params = 0x10000100;
  58
  59 /* kk - this speeds up your boot a quite a bit.  However to make it
  60  *  work, you need make sure your kernel startup flush bug is fixed.
  61  *  ... rkw ...
  62  */
  63         icache_enable ();
  64
  65         flash__init ();
  66         ether__init ();
  67         return 0;
  68 }
  69
  70
  71 int misc_init_r (void)
  72 {
  73         /* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */
  74         /* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */
  75
  76         /* setup gpio direction to match board (no floats!) */
  77         /**gdir = 0xCFF9; */
  78         /**mdir = 0x103F; */
  79
  80         return (0);
  81 }
  82
  83 /******************************
  84  Routine:
  85  Description:
  86 ******************************/
  87 static void flash__init (void)
  88 {
  89 #define CS0_CHIP_SELECT_REG 0xfffecc10
  90 #define CS3_CHIP_SELECT_REG 0xfffecc1c
  91 #define EMIFS_GlB_Config_REG 0xfffecc0c
  92
  93         {
  94                 unsigned int regval;
  95
  96                 regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
  97                 regval = regval | 0x0001;       /* Turn off write protection for flash devices. */
  98                 if (regval & 0x0002) {
  99                         regval = regval & 0xfffd;       /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */
 100                         /* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */
 101                         /* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */
 102                         /* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */
 103                 }
 104                 *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
 105         }
 106 }
 107
 108
 109 /******************************
 110  Routine:
 111  Description:
 112 ******************************/
 113 static void ether__init (void)
 114 {
 115 #define ETH_CONTROL_REG 0x0800000b
 116         /* take the Ethernet controller out of reset and wait
 117          * for the EEPROM load to complete.
 118          */
 119         *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
 120         udelay (3);
 121 }
 122
 123
 124 int dram_init (void)
 125 {
 126         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 127         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 128
 129         return 0;
 130 }
 131
 132 #ifdef CONFIG_CMD_NET
 133 int board_eth_init(bd_t *bis)
 134 {
 135         int rc = 0;
 136 #ifdef CONFIG_LAN91C96
 137         rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
 138 #endif
 139         return rc;
 140 }
 141 #endif