board/ti/omap730p2/lowlevel_init.S

   1 /*
   2  * Board specific setup info
   3  *
   4  * (C) Copyright 2003-2004
   5  *
   6  * Texas Instruments, <www.ti.com>
   7  * Kshitij Gupta <Kshitij@ti.com>
   8  *
   9  * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
  10  *
  11  * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
  12  * (http://www.mpc-data.co.uk)
  13  *
  14  * TODO : Tidy up and change to use system register defines
  15  *        from omap730.h where possible.
  16  *
  17  * SPDX-License-Identifier:     GPL-2.0+
  18  */
  19
  20 #include <config.h>
  21 #include <version.h>
  22
  23 #if defined(CONFIG_OMAP730)
  24 #include <./configs/omap730.h>
  25 #endif
  26
  27 _TEXT_BASE:
  28         .word   CONFIG_SYS_TEXT_BASE    /* sdram load addr from config.mk */
  29
  30 .globl lowlevel_init
  31 lowlevel_init:
  32         /* Save callers address in r11 - r11 must never be modified */
  33         mov r11, lr
  34
  35         /*------------------------------------------------------*
  36          *mask all IRQs by setting all bits in the INTMR default*
  37          *------------------------------------------------------*/
  38         mov     r1,     #0xffffffff
  39         ldr     r0,     =REG_IHL1_MIR
  40         str     r1,     [r0]
  41         ldr     r0,     =REG_IHL2_MIR
  42         str     r1,     [r0]
  43
  44         /*------------------------------------------------------*
  45          * Set up ARM CLM registers (IDLECT1)                   *
  46          *------------------------------------------------------*/
  47         ldr     r0,     REG_ARM_IDLECT1
  48         ldr     r1,     VAL_ARM_IDLECT1
  49         str     r1,     [r0]
  50
  51         /*------------------------------------------------------*
  52          * Set up ARM CLM registers (IDLECT2)                   *
  53          *------------------------------------------------------*/
  54         ldr     r0,     REG_ARM_IDLECT2
  55         ldr     r1,     VAL_ARM_IDLECT2
  56         str     r1,     [r0]
  57
  58         /*------------------------------------------------------*
  59          * Set up ARM CLM registers (IDLECT3)                   *
  60          *------------------------------------------------------*/
  61         ldr     r0,     REG_ARM_IDLECT3
  62         ldr     r1,     VAL_ARM_IDLECT3
  63         str     r1,     [r0]
  64
  65
  66         mov     r1,     #0x01           /* PER_EN bit */
  67         ldr     r0,     REG_ARM_RSTCT2
  68         strh    r1,     [r0]            /* CLKM; Peripheral reset. */
  69
  70         /* Set CLKM to Sync-Scalable    */
  71         /* I supposedly need to enable the dsp clock before switching */
  72         mov     r1,     #0x1000
  73         ldr     r0,     REG_ARM_SYSST
  74         strh    r1,     [r0]
  75         mov     r0,     #0x400
  76 1:
  77         subs    r0,     r0,     #0x1    /* wait for any bubbles to finish */
  78         bne     1b
  79         ldr     r1,     VAL_ARM_CKCTL
  80         ldr     r0,     REG_ARM_CKCTL
  81         strh    r1,     [r0]
  82
  83         /* a few nops to let settle */
  84         nop
  85         nop
  86         nop
  87         nop
  88         nop
  89         nop
  90         nop
  91         nop
  92         nop
  93         nop
  94
  95         /* setup DPLL 1 */
  96         /* Ramp up the clock to 96Mhz */
  97         ldr     r1,     VAL_DPLL1_CTL
  98         ldr     r0,     REG_DPLL1_CTL
  99         strh    r1,     [r0]
 100         ands    r1,     r1,     #0x10   /* Check if PLL is enabled. */
 101         beq     lock_end        /* Do not look for lock if BYPASS selected */
 102 2:
 103         ldrh    r1,     [r0]
 104         ands    r1,     r1,     #0x01   /*      Check the LOCK bit.*/
 105         beq 2b                  /*      loop until bit goes hi. */
 106 lock_end:
 107
 108         /*------------------------------------------------------*
 109          * Turn off the watchdog during init...                 *
 110          *------------------------------------------------------*/
 111         ldr     r0,     REG_WATCHDOG
 112         ldr     r1,     WATCHDOG_VAL1
 113         str     r1,     [r0]
 114         ldr     r1,     WATCHDOG_VAL2
 115         str     r1,     [r0]
 116         ldr     r0,     REG_WSPRDOG
 117         ldr     r1,     WSPRDOG_VAL1
 118         str     r1,     [r0]
 119         ldr     r0,     REG_WWPSDOG
 120
 121 watch1Wait:
 122         ldr     r1,     [r0]
 123         tst     r1,     #0x10
 124         bne     watch1Wait
 125
 126         ldr     r0,     REG_WSPRDOG
 127         ldr     r1,     WSPRDOG_VAL2
 128         str     r1,     [r0]
 129         ldr     r0,     REG_WWPSDOG
 130 watch2Wait:
 131         ldr     r1,     [r0]
 132         tst     r1,     #0x10
 133         bne     watch2Wait
 134
 135         /* Set memory timings corresponding to the new clock speed */
 136
 137         /* Check execution location to determine current execution location
 138          * and branch to appropriate initialization code.
 139          */
 140         /* Compare physical SDRAM base & current execution location. */
 141         and     r0, pc, #0xF0000000
 142         /* Compare. */
 143         cmp     r0, #0
 144         /* Skip over EMIF-fast initialization if running from SDRAM. */
 145         bne     skip_sdram
 146
 147         /*
 148         * Delay for SDRAM initialization.
 149         */
 150         mov     r3,     #0x1800         /* value should be checked */
 151 3:
 152         subs    r3,     r3,     #0x1    /* Decrement count */
 153         bne     3b
 154
 155         ldr     r0,     REG_SDRAM_CONFIG
 156         ldr     r1,     SDRAM_CONFIG_VAL
 157         str     r1,     [r0]
 158
 159         ldr     r0,     REG_SDRAM_MRS_LEGACY
 160         ldr     r1,     SDRAM_MRS_VAL
 161         str     r1,     [r0]
 162
 163 skip_sdram:
 164
 165 common_tc:
 166         /* slow interface */
 167         ldr     r1,     VAL_TC_EMIFS_CS0_CONFIG
 168         ldr     r0,     REG_TC_EMIFS_CS0_CONFIG
 169         str     r1,     [r0] /* Chip Select 0 */
 170
 171         ldr     r1,     VAL_TC_EMIFS_CS1_CONFIG
 172         ldr     r0,     REG_TC_EMIFS_CS1_CONFIG
 173         str     r1,     [r0] /* Chip Select 1 */
 174         ldr     r1,     VAL_TC_EMIFS_CS2_CONFIG
 175         ldr     r0,     REG_TC_EMIFS_CS2_CONFIG
 176         str     r1,     [r0] /* Chip Select 2 */
 177         ldr     r1,     VAL_TC_EMIFS_CS3_CONFIG
 178         ldr     r0,     REG_TC_EMIFS_CS3_CONFIG
 179         str     r1,     [r0] /* Chip Select 3 */
 180
 181         /* 48MHz clock request for UART1 */
 182         ldr     r1,     PERSEUS2_CONFIG_BASE
 183         ldrh    r0,     [r1, #CONFIG_PCC_CONF]
 184         orr     r0,     r0, #CONF_MOD_UART1_CLK_MODE_R
 185         strh    r0,     [r1, #CONFIG_PCC_CONF]
 186
 187         /* Initialize public and private rheas
 188          *  - set access factor 2 on both rhea / strobe
 189          *  - disable write buffer on strb0, enable write buffer on strb1
 190          */
 191
 192         ldr     R0,     REG_RHEA_PUB_CTL
 193         ldr     R1,     REG_RHEA_PRIV_CTL
 194         ldr     R2,     VAL_RHEA_CTL
 195         strh    R2,     [R0]
 196         strh    R2,     [R1]
 197         mov     R3,     #2          /* disable write buffer on strb0, enable write buffer on strb1 */
 198         strh    R3,     [R0, #0x08]     /* arm rhea control reg */
 199         strh    R3,     [R1, #0x08]
 200
 201         /* enable IRQ and FIQ */
 202
 203         mrs     r4,     CPSR
 204         bic     r4,     r4, #IRQ_MASK
 205         bic     r4,     r4, #FIQ_MASK
 206         msr     CPSR,   r4
 207
 208         /* set TAP CONF to TRI EMULATION */
 209
 210         ldr     r1,     [r0, #CONFIG_MODE2]
 211         bic     r1,     r1, #0x18
 212         orr     r1,     r1, #0x10
 213         str     r1,     [r0, #CONFIG_MODE2]
 214
 215         /* set tdbgen to 1 */
 216
 217         ldr     r0,     PERSEUS2_CONFIG_BASE
 218         ldr     r1,     [r0, #CONFIG_MODE1]
 219         mov     r2,     #0x10000
 220         orr     r1,     r1, r2
 221         str     r1,     [r0, #CONFIG_MODE1]
 222
 223 #ifdef CONFIG_P2_OMAP1610
 224         /* inserting additional 2 clock cycle hold time for LAN */
 225         ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
 226         ldr     r1,     VAL_TC_EMIFS_CS1_ADVANCED
 227         str     r1,     [r0]
 228 #endif
 229         /* Start MPU Timer 1 */
 230         ldr     r0,     REG_MPU_LOAD_TIMER
 231         ldr     r1,     VAL_MPU_LOAD_TIMER
 232         str     r1,     [r0]
 233
 234         ldr     r0,     REG_MPU_CNTL_TIMER
 235         ldr     r1,     VAL_MPU_CNTL_TIMER
 236         str     r1,     [r0]
 237
 238         /* back to arch calling code */
 239         mov     pc,     r11
 240
 241         /* the literal pools origin */
 242         .ltorg
 243
 244 REG_TC_EMIFS_CONFIG:            /* 32 bits */
 245         .word 0xfffecc0c
 246 REG_TC_EMIFS_CS0_CONFIG:        /* 32 bits */
 247         .word 0xfffecc10
 248 REG_TC_EMIFS_CS1_CONFIG:        /* 32 bits */
 249         .word 0xfffecc14
 250 REG_TC_EMIFS_CS2_CONFIG:        /* 32 bits */
 251         .word 0xfffecc18
 252 REG_TC_EMIFS_CS3_CONFIG:        /* 32 bits */
 253         .word 0xfffecc1c
 254
 255 #ifdef CONFIG_P2_OMAP730
 256 REG_TC_EMIFS_CS1_ADVANCED:      /* 32 bits */
 257         .word 0xfffecc54
 258 #endif
 259
 260 /* MPU clock/reset/power mode control registers */
 261 REG_ARM_CKCTL:                  /* 16 bits */
 262         .word 0xfffece00
 263
 264 REG_ARM_IDLECT3:                /* 16 bits */
 265         .word 0xfffece24
 266 REG_ARM_IDLECT2:                /* 16 bits */
 267         .word 0xfffece08
 268 REG_ARM_IDLECT1:                /* 16 bits */
 269         .word 0xfffece04
 270
 271 REG_ARM_RSTCT2:                 /* 16 bits */
 272         .word 0xfffece14
 273 REG_ARM_SYSST:                  /* 16 bits */
 274         .word 0xfffece18
 275 /* DPLL control registers */
 276 REG_DPLL1_CTL:                  /* 16 bits */
 277         .word 0xfffecf00
 278
 279 /* Watch Dog register */
 280 /* secure watchdog stop */
 281 REG_WSPRDOG:
 282         .word 0xfffeb048
 283 /* watchdog write pending */
 284 REG_WWPSDOG:
 285         .word 0xfffeb034
 286
 287 WSPRDOG_VAL1:
 288         .word 0x0000aaaa
 289 WSPRDOG_VAL2:
 290         .word 0x00005555
 291
 292 /* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
 293  counter @8192 rows, 10 ns, 8 burst */
 294 REG_SDRAM_CONFIG:
 295         .word 0xfffecc20
 296
 297 REG_SDRAM_MRS_LEGACY:
 298         .word 0xfffecc24
 299
 300 REG_WATCHDOG:
 301         .word 0xfffec808
 302
 303 REG_MPU_LOAD_TIMER:
 304         .word 0xfffec504
 305 REG_MPU_CNTL_TIMER:
 306         .word 0xfffec500
 307
 308 /* Public and private rhea bridge registers definition */
 309
 310 REG_RHEA_PUB_CTL:
 311         .word 0xFFFECA00
 312
 313 REG_RHEA_PRIV_CTL:
 314         .word 0xFFFED300
 315
 316 /* EMIFF SDRAM Configuration register
 317    - self refresh disable
 318    - auto refresh enabled
 319    - SDRAM type 64 Mb, 16 bits bus 4 banks
 320    - power down enabled
 321    - SDRAM clock disabled
 322  */
 323 SDRAM_CONFIG_VAL:
 324         .word 0x0C017DF4
 325
 326 /* Burst full page length ; cas latency = 3 */
 327 SDRAM_MRS_VAL:
 328         .word 0x00000037
 329
 330 VAL_ARM_CKCTL:
 331         .word 0x6505
 332 VAL_DPLL1_CTL:
 333         .word 0x3412
 334
 335 #ifdef CONFIG_P2_OMAP730
 336 VAL_TC_EMIFS_CS0_CONFIG:
 337         .word 0x0000FFF3
 338 VAL_TC_EMIFS_CS1_CONFIG:
 339         .word 0x00004278
 340 VAL_TC_EMIFS_CS2_CONFIG:
 341         .word 0x00004278
 342 VAL_TC_EMIFS_CS3_CONFIG:
 343         .word 0x00004278
 344 VAL_TC_EMIFS_CS1_ADVANCED:
 345         .word 0x00000022
 346 #endif
 347
 348 VAL_ARM_IDLECT1:
 349         .word 0x00000400
 350 VAL_ARM_IDLECT2:
 351         .word 0x00000886
 352 VAL_ARM_IDLECT3:
 353         .word 0x00000015
 354
 355 WATCHDOG_VAL1:
 356         .word 0x000000f5
 357 WATCHDOG_VAL2:
 358         .word 0x000000a0
 359
 360 VAL_MPU_LOAD_TIMER:
 361         .word 0xffffffff
 362 VAL_MPU_CNTL_TIMER:
 363         .word 0xffffffa1
 364
 365 VAL_RHEA_CTL:
 366         .word                   0xFF22
 367
 368 /* Config Register vals */
 369 PERSEUS2_CONFIG_BASE:
 370         .word                   0xFFFE1000
 371
 372 .equ    CONFIG_PCC_CONF,        0xB4
 373 .equ    CONFIG_MODE1,           0x10
 374 .equ    CONFIG_MODE2,           0x14
 375 .equ    CONF_MOD_UART1_CLK_MODE_R,      0x0A
 376
 377 /* misc values */
 378 .equ    IRQ_MASK,               0x80           /* IRQ mask value */
 379 .equ    FIQ_MASK,               0x40           /* FIQ mask value */