1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
6 * Antoine Tenart, <atenart@adeneo-embedded.com>
12 #include <asm/cache.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/ddr_defs.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/mmc_host_def.h>
20 #include <asm/arch/mem.h>
21 #include <asm/arch/mux.h>
23 DECLARE_GLOBAL_DATA_PTR
;
27 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
28 #if defined(CONFIG_MTD_RAW_NAND)
34 int board_eth_init(bd_t
*bis
)
37 uint32_t mac_hi
, mac_lo
;
38 struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
40 if (!eth_env_get_enetaddr("ethaddr", mac_addr
)) {
41 printf("<ethaddr> not set. Reading from E-fuse\n");
42 /* try reading mac address from efuse */
43 mac_lo
= readl(&cdev
->macid0l
);
44 mac_hi
= readl(&cdev
->macid0h
);
45 mac_addr
[0] = mac_hi
& 0xFF;
46 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
47 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
48 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
49 mac_addr
[4] = mac_lo
& 0xFF;
50 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
52 if (is_valid_ethaddr(mac_addr
))
53 eth_env_set_enetaddr("ethaddr", mac_addr
);
55 printf("Unable to read MAC address. Set <ethaddr>\n");
61 #ifdef CONFIG_SPL_BUILD
62 static struct module_pin_mux mmc_pin_mux
[] = {
63 { OFFSET(pincntl157
), PULLDOWN_EN
| PULLUDDIS
| MODE(0x0) },
64 { OFFSET(pincntl158
), PULLDOWN_EN
| PULLUDEN
| MODE(0x0) },
65 { OFFSET(pincntl159
), PULLUP_EN
| PULLUDDIS
| MODE(0x0) },
66 { OFFSET(pincntl160
), PULLUP_EN
| PULLUDDIS
| MODE(0x0) },
67 { OFFSET(pincntl161
), PULLUP_EN
| PULLUDDIS
| MODE(0x0) },
68 { OFFSET(pincntl162
), PULLUP_EN
| PULLUDDIS
| MODE(0x0) },
69 { OFFSET(pincntl163
), PULLUP_EN
| PULLUDDIS
| MODE(0x0) },
73 void set_uart_mux_conf(void) {}
75 void set_mux_conf_regs(void)
77 configure_module_pin_mux(mmc_pin_mux
);
81 * EMIF Paramters. Refer the EMIF register documentation and the
82 * memory datasheet for details. This is for 796 MHz.
84 #define EMIF_TIM1 0x1779C9FE
85 #define EMIF_TIM2 0x50608074
86 #define EMIF_TIM3 0x009F857F
87 #define EMIF_SDREF 0x10001841
88 #define EMIF_SDCFG 0x62A73832
89 #define EMIF_PHYCFG 0x00000110
90 static const struct emif_regs ddr3_emif_regs
= {
91 .sdram_config
= EMIF_SDCFG
,
92 .ref_ctrl
= EMIF_SDREF
,
93 .sdram_tim1
= EMIF_TIM1
,
94 .sdram_tim2
= EMIF_TIM2
,
95 .sdram_tim3
= EMIF_TIM3
,
96 .emif_ddr_phy_ctlr_1
= EMIF_PHYCFG
,
99 static const struct cmd_control ddr3_ctrl
= {
100 .cmd0csratio
= 0x100,
101 .cmd0iclkout
= 0x001,
102 .cmd1csratio
= 0x100,
103 .cmd1iclkout
= 0x001,
104 .cmd2csratio
= 0x100,
105 .cmd2iclkout
= 0x001,
108 /* These values are obtained from the CCS app */
109 #define RD_DQS_GATE (0x1B3)
110 #define RD_DQS (0x35)
111 #define WR_DQS (0x93)
112 static struct ddr_data ddr3_data
= {
113 .datardsratio0
= ((RD_DQS
<<10) | (RD_DQS
<<0)),
114 .datawdsratio0
= ((WR_DQS
<<10) | (WR_DQS
<<0)),
115 .datawiratio0
= ((0x20<<10) | 0x20<<0),
116 .datagiratio0
= ((0x20<<10) | 0x20<<0),
117 .datafwsratio0
= ((RD_DQS_GATE
<<10) | (RD_DQS_GATE
<<0)),
118 .datawrsratio0
= (((WR_DQS
+0x40)<<10) | ((WR_DQS
+0x40)<<0)),
121 static const struct dmm_lisa_map_regs evm_lisa_map_regs
= {
122 .dmm_lisa_map_0
= 0x00000000,
123 .dmm_lisa_map_1
= 0x00000000,
124 .dmm_lisa_map_2
= 0x80640300,
125 .dmm_lisa_map_3
= 0xC0640320,
128 void sdram_init(void)
131 * Pass in our DDR3 config information and that we have 2 EMIFs to
134 config_ddr(&ddr3_data
, &ddr3_ctrl
, &ddr3_emif_regs
,
135 &evm_lisa_map_regs
, 2);
137 #endif /* CONFIG_SPL_BUILD */