1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016-2018 Toradex AG
6 #include <asm/arch/clock.h>
7 #include <asm/arch/crm_regs.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/mx7-pins.h>
10 #include <asm/arch/sys_proto.h>
12 #include <asm/mach-imx/iomux-v3.h>
16 #include <dm/platform_data/serial_mxc.h>
17 #include <fdt_support.h>
18 #include <fsl_esdhc.h>
19 #include <jffs2/load_kernel.h>
20 #include <linux/sizes.h>
25 #include <power/pmic.h>
26 #include <power/rn5t567_pmic.h>
28 #include <usb/ehci-ci.h>
29 #include "../common/tdx-common.h"
31 DECLARE_GLOBAL_DATA_PTR
;
33 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
34 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
36 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
37 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
39 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
41 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
42 PAD_CTL_DSE_3P3V_49OHM)
44 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
46 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
48 #define USB_CDET_GPIO IMX_GPIO_NR(7, 14)
52 gd
->ram_size
= get_ram_size((void *)PHYS_SDRAM
, imx_ddr_size());
57 static iomux_v3_cfg_t
const uart1_pads
[] = {
58 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
59 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
60 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS
| MUX_PAD_CTRL(UART_PAD_CTRL
),
61 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS
| MUX_PAD_CTRL(UART_PAD_CTRL
),
64 #ifdef CONFIG_USB_EHCI_MX7
65 static iomux_v3_cfg_t
const usb_cdet_pads
[] = {
66 MX7D_PAD_ENET1_CRS__GPIO7_IO14
| MUX_PAD_CTRL(NO_PAD_CTRL
),
70 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
71 static iomux_v3_cfg_t
const gpmi_pads
[] = {
72 MX7D_PAD_SD3_DATA0__NAND_DATA00
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
73 MX7D_PAD_SD3_DATA1__NAND_DATA01
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
74 MX7D_PAD_SD3_DATA2__NAND_DATA02
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
75 MX7D_PAD_SD3_DATA3__NAND_DATA03
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
76 MX7D_PAD_SD3_DATA4__NAND_DATA04
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
77 MX7D_PAD_SD3_DATA5__NAND_DATA05
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
78 MX7D_PAD_SD3_DATA6__NAND_DATA06
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
79 MX7D_PAD_SD3_DATA7__NAND_DATA07
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
80 MX7D_PAD_SD3_CLK__NAND_CLE
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
81 MX7D_PAD_SD3_CMD__NAND_ALE
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
82 MX7D_PAD_SD3_STROBE__NAND_RE_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
83 MX7D_PAD_SD3_RESET_B__NAND_WE_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
84 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
85 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
86 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B
| MUX_PAD_CTRL(NAND_PAD_READY0_CTRL
),
89 static void setup_gpmi_nand(void)
91 imx_iomux_v3_setup_multiple_pads(gpmi_pads
, ARRAY_SIZE(gpmi_pads
));
93 /* NAND_USDHC_BUS_CLK is set in rom */
98 #ifdef CONFIG_VIDEO_MXS
99 static iomux_v3_cfg_t
const lcd_pads
[] = {
100 MX7D_PAD_LCD_CLK__LCD_CLK
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
101 MX7D_PAD_LCD_ENABLE__LCD_ENABLE
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
102 MX7D_PAD_LCD_HSYNC__LCD_HSYNC
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
103 MX7D_PAD_LCD_VSYNC__LCD_VSYNC
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
104 MX7D_PAD_LCD_DATA00__LCD_DATA0
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
105 MX7D_PAD_LCD_DATA01__LCD_DATA1
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
106 MX7D_PAD_LCD_DATA02__LCD_DATA2
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
107 MX7D_PAD_LCD_DATA03__LCD_DATA3
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
108 MX7D_PAD_LCD_DATA04__LCD_DATA4
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
109 MX7D_PAD_LCD_DATA05__LCD_DATA5
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
110 MX7D_PAD_LCD_DATA06__LCD_DATA6
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
111 MX7D_PAD_LCD_DATA07__LCD_DATA7
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
112 MX7D_PAD_LCD_DATA08__LCD_DATA8
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
113 MX7D_PAD_LCD_DATA09__LCD_DATA9
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
114 MX7D_PAD_LCD_DATA10__LCD_DATA10
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
115 MX7D_PAD_LCD_DATA11__LCD_DATA11
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
116 MX7D_PAD_LCD_DATA12__LCD_DATA12
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
117 MX7D_PAD_LCD_DATA13__LCD_DATA13
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
118 MX7D_PAD_LCD_DATA14__LCD_DATA14
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
119 MX7D_PAD_LCD_DATA15__LCD_DATA15
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
120 MX7D_PAD_LCD_DATA16__LCD_DATA16
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
121 MX7D_PAD_LCD_DATA17__LCD_DATA17
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
124 static iomux_v3_cfg_t
const backlight_pads
[] = {
126 MX7D_PAD_SD1_WP__GPIO5_IO1
| MUX_PAD_CTRL(NO_PAD_CTRL
),
127 /* Backlight PWM<A> (multiplexed pin) */
128 MX7D_PAD_GPIO1_IO08__GPIO1_IO8
| MUX_PAD_CTRL(NO_PAD_CTRL
),
129 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21
| MUX_PAD_CTRL(NO_PAD_CTRL
),
132 #define GPIO_BL_ON IMX_GPIO_NR(5, 1)
133 #define GPIO_PWM_A IMX_GPIO_NR(1, 8)
135 static int setup_lcd(void)
137 imx_iomux_v3_setup_multiple_pads(lcd_pads
, ARRAY_SIZE(lcd_pads
));
139 imx_iomux_v3_setup_multiple_pads(backlight_pads
, ARRAY_SIZE(backlight_pads
));
142 gpio_request(GPIO_BL_ON
, "BL_ON");
143 gpio_direction_output(GPIO_BL_ON
, 1);
145 /* Set PWM<A> to full brightness (assuming inversed polarity) */
146 gpio_request(GPIO_PWM_A
, "PWM<A>");
147 gpio_direction_output(GPIO_PWM_A
, 0);
154 * Backlight off before OS handover
156 void board_preboot_os(void)
158 gpio_direction_output(GPIO_PWM_A
, 1);
159 gpio_direction_output(GPIO_BL_ON
, 0);
162 #ifdef CONFIG_FEC_MXC
163 static iomux_v3_cfg_t
const fec1_pads
[] = {
164 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
165 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1
| MUX_PAD_CTRL(ENET_PAD_CTRL
) | MUX_MODE_SION
,
167 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
169 MX7D_PAD_SD2_CD_B__ENET1_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL_MII
),
170 MX7D_PAD_SD2_WP__ENET1_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL_MII
),
171 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
172 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
173 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
174 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
175 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
176 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
177 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
180 static void setup_iomux_fec(void)
182 imx_iomux_v3_setup_multiple_pads(fec1_pads
, ARRAY_SIZE(fec1_pads
));
186 static void setup_iomux_uart(void)
188 imx_iomux_v3_setup_multiple_pads(uart1_pads
, ARRAY_SIZE(uart1_pads
));
191 #ifdef CONFIG_FEC_MXC
192 int board_eth_init(bd_t
*bis
)
198 ret
= fecmxc_initialize_multi(bis
, 0,
199 CONFIG_FEC_MXC_PHYADDR
, IMX_FEC_BASE
);
201 printf("FEC1 MXC: %s:failed\n", __func__
);
206 static int setup_fec(void)
208 struct iomuxc_gpr_base_regs
*const iomuxc_gpr_regs
209 = (struct iomuxc_gpr_base_regs
*)IOMUXC_GPR_BASE_ADDR
;
211 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
213 * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
214 * and output it on the pin
216 clrsetbits_le32(&iomuxc_gpr_regs
->gpr
[1],
217 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK
,
218 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK
);
220 /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
221 clrsetbits_le32(&iomuxc_gpr_regs
->gpr
[1],
222 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK
,
223 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK
);
226 return set_clk_enet(ENET_50MHZ
);
229 int board_phy_config(struct phy_device
*phydev
)
231 if (phydev
->drv
->config
)
232 phydev
->drv
->config(phydev
);
237 int board_early_init_f(void)
246 /* address of boot parameters */
247 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
249 #ifdef CONFIG_FEC_MXC
253 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
257 #ifdef CONFIG_VIDEO_MXS
261 #ifdef CONFIG_USB_EHCI_MX7
262 imx_iomux_v3_setup_multiple_pads(usb_cdet_pads
, ARRAY_SIZE(usb_cdet_pads
));
263 gpio_request(USB_CDET_GPIO
, "usb-cdet-gpio");
269 #ifdef CONFIG_DM_PMIC
270 int power_init_board(void)
277 ret
= pmic_get("rn5t567", &dev
);
280 ver
= pmic_reg_read(dev
, RN5T567_LSIVER
);
281 reg
= pmic_reg_read(dev
, RN5T567_OTPVER
);
283 printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver
, reg
);
285 /* set judge and press timer of N_OE to minimal values */
286 pmic_clrsetbits(dev
, RN5T567_NOETIMSETCNT
, 0x7, 0);
288 /* configure sleep slot for 3.3V Ethernet */
289 reg
= pmic_reg_read(dev
, RN5T567_LDO1_SLOT
);
290 reg
= (reg
& 0xf0) | reg
>> 4;
291 pmic_reg_write(dev
, RN5T567_LDO1_SLOT
, reg
);
293 /* disable DCDC2 discharge to avoid backfeeding through VFB2 */
294 pmic_clrsetbits(dev
, RN5T567_DC2CTL
, 0x2, 0);
296 /* configure sleep slot for ARM rail */
297 reg
= pmic_reg_read(dev
, RN5T567_DC2_SLOT
);
298 reg
= (reg
& 0xf0) | reg
>> 4;
299 pmic_reg_write(dev
, RN5T567_DC2_SLOT
, reg
);
301 /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
302 pmic_clrsetbits(dev
, RN5T567_LDODIS1
, 0x2, 0);
307 void reset_cpu(ulong addr
)
311 pmic_get("rn5t567", &dev
);
313 /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
314 pmic_reg_write(dev
, RN5T567_REPCNT
, 0x1);
315 pmic_reg_write(dev
, RN5T567_SLPCNT
, 0x1);
318 * Re-power factor detection on PMIC side is not instant. 1ms
319 * proved to be enough time until reset takes effect.
327 printf("Model: Toradex Colibri iMX7%c\n",
328 is_cpu_type(MXC_CPU_MX7D
) ? 'D' : 'S');
333 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
334 int ft_board_setup(void *blob
, bd_t
*bd
)
336 #if defined(CONFIG_FDT_FIXUP_PARTITIONS)
337 static const struct node_info nodes
[] = {
338 { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND
, }, /* NAND flash */
339 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND
, },
342 /* Update partition nodes using info from mtdparts env var */
343 puts(" Updating MTD partitions...\n");
344 fdt_fixup_mtdparts(blob
, nodes
, ARRAY_SIZE(nodes
));
347 return ft_common_board_setup(blob
, bd
);
351 #ifdef CONFIG_USB_EHCI_MX7
352 static iomux_v3_cfg_t
const usb_otg2_pads
[] = {
353 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR
| MUX_PAD_CTRL(NO_PAD_CTRL
),
356 int board_ehci_hcd_init(int port
)
362 if (is_cpu_type(MXC_CPU_MX7S
))
365 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads
,
366 ARRAY_SIZE(usb_otg2_pads
));
374 int board_usb_phy_mode(int port
)
378 if (gpio_get_value(USB_CDET_GPIO
))
379 return USB_INIT_DEVICE
;
381 return USB_INIT_HOST
;
384 return USB_INIT_HOST
;