board/toradex/colibri_pxa270/colibri_pxa270.c

   1 /*
   2  * Toradex Colibri PXA270 Support
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/regs-mmc.h>
  12 #include <asm/arch/pxa.h>
  13 #include <netdev.h>
  14 #include <asm/io.h>
  15 #include <serial.h>
  16 #include <usb.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 int board_init(void)
  21 {
  22         /* We have RAM, disable cache */
  23         dcache_disable();
  24         icache_disable();
  25
  26         /* arch number of vpac270 */
  27         gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
  28
  29         /* adress of boot parameters */
  30         gd->bd->bi_boot_params = 0xa0000100;
  31
  32         return 0;
  33 }
  34
  35 int dram_init(void)
  36 {
  37         pxa2xx_dram_init();
  38         gd->ram_size = PHYS_SDRAM_1_SIZE;
  39         return 0;
  40 }
  41
  42 #ifdef  CONFIG_CMD_USB
  43 int board_usb_init(int index, enum board_usb_init_type init)
  44 {
  45         writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
  46                 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
  47                 UHCHR);
  48
  49         writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  50
  51         while (UHCHR & UHCHR_FSBIR)
  52                 ;
  53
  54         writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
  55         writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
  56
  57         /* Clear any OTG Pin Hold */
  58         if (readl(PSSR) & PSSR_OTGPH)
  59                 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
  60
  61         writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
  62         writel(readl(UHCRHDA) | 0x100, UHCRHDA);
  63
  64         /* Set port power control mask bits, only 3 ports. */
  65         writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
  66
  67         /* enable port 2 */
  68         writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
  69                 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
  70
  71         return 0;
  72 }
  73
  74 int board_usb_cleanup(int index, enum board_usb_init_type init)
  75 {
  76         return 0;
  77 }
  78
  79 void usb_board_stop(void)
  80 {
  81         writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
  82         udelay(11);
  83         writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
  84
  85         writel(readl(UHCCOMS) | 1, UHCCOMS);
  86         udelay(10);
  87
  88         writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
  89
  90         return;
  91 }
  92 #endif
  93
  94 #ifdef CONFIG_DRIVER_DM9000
  95 int board_eth_init(bd_t *bis)
  96 {
  97         return dm9000_initialize(bis);
  98 }
  99 #endif
 100
 101 #ifdef  CONFIG_CMD_MMC
 102 int board_mmc_init(bd_t *bis)
 103 {
 104         pxa_mmc_register(0);
 105         return 0;
 106 }
 107 #endif