2 * Copyright (c) 2013-2014, Stefan Agner
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _PINMUX_CONFIG_COLIBRI_T30_H_
8 #define _PINMUX_CONFIG_COLIBRI_T30_H_
10 #define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
12 .pingrp = PMUX_PINGRP_##_pingrp, \
13 .func = PMUX_FUNC_##_mux, \
14 .pull = PMUX_PULL_##_pull, \
15 .tristate = PMUX_TRI_##_tri, \
16 .io = PMUX_PIN_##_io, \
17 .lock = PMUX_PIN_LOCK_DEFAULT, \
18 .od = PMUX_PIN_OD_DEFAULT, \
19 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
22 #define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
24 .pingrp = PMUX_PINGRP_##_pingrp, \
25 .func = PMUX_FUNC_##_mux, \
26 .pull = PMUX_PULL_##_pull, \
27 .tristate = PMUX_TRI_##_tri, \
28 .io = PMUX_PIN_##_io, \
29 .lock = PMUX_PIN_LOCK_##_lock, \
30 .od = PMUX_PIN_OD_##_od, \
31 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
34 #define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
36 .pingrp = PMUX_PINGRP_##_pingrp, \
37 .func = PMUX_FUNC_##_mux, \
38 .pull = PMUX_PULL_##_pull, \
39 .tristate = PMUX_TRI_##_tri, \
40 .io = PMUX_PIN_##_io, \
41 .lock = PMUX_PIN_LOCK_##_lock, \
42 .od = PMUX_PIN_OD_DEFAULT, \
43 .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
46 #define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
48 .drvgrp = PMUX_DRVGRP_##_drvgrp, \
53 .lpmd = PMUX_LPMD_##_lpmd, \
54 .schmt = PMUX_SCHMT_##_schmt, \
55 .hsm = PMUX_HSM_##_hsm, \
58 static struct pmux_pingrp_config tegra3_pinmux_common
[] = {
60 DEFAULT_PINMUX(SDMMC1_CLK_PZ0
, RSVD1
, NORMAL
, NORMAL
, INPUT
),
61 DEFAULT_PINMUX(SDMMC1_CMD_PZ1
, RSVD1
, NORMAL
, NORMAL
, INPUT
),
62 DEFAULT_PINMUX(SDMMC1_DAT3_PY4
, RSVD1
, NORMAL
, NORMAL
, INPUT
),
63 DEFAULT_PINMUX(SDMMC1_DAT2_PY5
, RSVD1
, NORMAL
, NORMAL
, INPUT
),
64 DEFAULT_PINMUX(SDMMC1_DAT1_PY6
, RSVD1
, NORMAL
, NORMAL
, INPUT
),
65 DEFAULT_PINMUX(SDMMC1_DAT0_PY7
, RSVD1
, NORMAL
, NORMAL
, INPUT
),
68 DEFAULT_PINMUX(SDMMC3_CLK_PA6
, SDMMC3
, NORMAL
, NORMAL
, INPUT
),
69 DEFAULT_PINMUX(SDMMC3_CMD_PA7
, SDMMC3
, UP
, NORMAL
, INPUT
),
70 DEFAULT_PINMUX(SDMMC3_DAT0_PB7
, SDMMC3
, UP
, NORMAL
, INPUT
),
71 DEFAULT_PINMUX(SDMMC3_DAT1_PB6
, SDMMC3
, UP
, NORMAL
, INPUT
),
72 DEFAULT_PINMUX(SDMMC3_DAT2_PB5
, SDMMC3
, UP
, NORMAL
, INPUT
),
73 DEFAULT_PINMUX(SDMMC3_DAT3_PB4
, SDMMC3
, UP
, NORMAL
, INPUT
),
74 DEFAULT_PINMUX(SDMMC3_DAT6_PD3
, RSVD1
, NORMAL
, NORMAL
, INPUT
),
75 DEFAULT_PINMUX(SDMMC3_DAT7_PD4
, RSVD1
, NORMAL
, NORMAL
, INPUT
),
77 /* SDMMC4 pinmux (eMMC) */
78 LV_PINMUX(SDMMC4_CLK_PCC4
, SDMMC4
, NORMAL
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
79 LV_PINMUX(SDMMC4_CMD_PT7
, SDMMC4
, UP
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
80 LV_PINMUX(SDMMC4_DAT0_PAA0
, SDMMC4
, UP
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
81 LV_PINMUX(SDMMC4_DAT1_PAA1
, SDMMC4
, UP
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
82 LV_PINMUX(SDMMC4_DAT2_PAA2
, SDMMC4
, UP
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
83 LV_PINMUX(SDMMC4_DAT3_PAA3
, SDMMC4
, UP
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
84 LV_PINMUX(SDMMC4_DAT4_PAA4
, SDMMC4
, UP
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
85 LV_PINMUX(SDMMC4_DAT5_PAA5
, SDMMC4
, UP
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
86 LV_PINMUX(SDMMC4_DAT6_PAA6
, SDMMC4
, UP
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
87 LV_PINMUX(SDMMC4_DAT7_PAA7
, SDMMC4
, UP
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
88 LV_PINMUX(SDMMC4_RST_N_PCC3
, RSVD1
, DOWN
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
91 I2C_PINMUX(GEN1_I2C_SCL_PC4
, I2C1
, NORMAL
, NORMAL
, INPUT
, DISABLE
, ENABLE
),
92 I2C_PINMUX(GEN1_I2C_SDA_PC5
, I2C1
, NORMAL
, NORMAL
, INPUT
, DISABLE
, ENABLE
),
95 DEFAULT_PINMUX(GEN2_I2C_SCL_PT5
, I2C2
, NORMAL
, NORMAL
, INPUT
),
96 DEFAULT_PINMUX(GEN2_I2C_SDA_PT6
, I2C2
, NORMAL
, NORMAL
, INPUT
),
98 /* I2C3 pinmux, muliplexed with KB_ROW13/KB_ROW14 */
99 I2C_PINMUX(CAM_I2C_SCL_PBB1
, I2C3
, NORMAL
, TRISTATE
, INPUT
, DISABLE
, ENABLE
),
100 I2C_PINMUX(CAM_I2C_SDA_PBB2
, I2C3
, NORMAL
, TRISTATE
, INPUT
, DISABLE
, ENABLE
),
103 I2C_PINMUX(DDC_SCL_PV4
, I2C4
, NORMAL
, NORMAL
, INPUT
, DISABLE
, ENABLE
),
104 I2C_PINMUX(DDC_SDA_PV5
, I2C4
, NORMAL
, NORMAL
, INPUT
, DISABLE
, ENABLE
),
106 /* Power I2C pinmux */
107 I2C_PINMUX(PWR_I2C_SCL_PZ6
, I2CPWR
, NORMAL
, NORMAL
, INPUT
, DISABLE
, ENABLE
),
108 I2C_PINMUX(PWR_I2C_SDA_PZ7
, I2CPWR
, NORMAL
, NORMAL
, INPUT
, DISABLE
, ENABLE
),
110 DEFAULT_PINMUX(ULPI_DATA0_PO1
, UARTA
, NORMAL
, NORMAL
, OUTPUT
),
111 /* UARTA RX, make sure we don't get input form a floating Pin */
112 DEFAULT_PINMUX(ULPI_DATA1_PO2
, UARTA
, UP
, NORMAL
, INPUT
),
113 DEFAULT_PINMUX(ULPI_DATA2_PO3
, UARTA
, NORMAL
, NORMAL
, INPUT
),
114 DEFAULT_PINMUX(ULPI_DATA3_PO4
, RSVD1
, NORMAL
, NORMAL
, INPUT
),
115 DEFAULT_PINMUX(ULPI_DATA4_PO5
, UARTA
, NORMAL
, NORMAL
, INPUT
),
116 DEFAULT_PINMUX(ULPI_DATA5_PO6
, UARTA
, NORMAL
, NORMAL
, INPUT
),
117 DEFAULT_PINMUX(ULPI_DATA6_PO7
, UARTA
, NORMAL
, NORMAL
, INPUT
),
118 DEFAULT_PINMUX(ULPI_DATA7_PO0
, UARTA
, NORMAL
, NORMAL
, OUTPUT
),
119 DEFAULT_PINMUX(ULPI_CLK_PY0
, SPI1
, NORMAL
, NORMAL
, INPUT
),
120 DEFAULT_PINMUX(ULPI_DIR_PY1
, SPI1
, NORMAL
, NORMAL
, INPUT
),
121 DEFAULT_PINMUX(ULPI_NXT_PY2
, SPI1
, NORMAL
, NORMAL
, INPUT
),
122 DEFAULT_PINMUX(ULPI_STP_PY3
, SPI1
, NORMAL
, NORMAL
, INPUT
),
123 DEFAULT_PINMUX(DAP3_FS_PP0
, I2S2
, NORMAL
, NORMAL
, INPUT
),
124 DEFAULT_PINMUX(DAP3_DIN_PP1
, I2S2
, NORMAL
, NORMAL
, INPUT
),
125 DEFAULT_PINMUX(DAP3_DOUT_PP2
, I2S2
, NORMAL
, NORMAL
, INPUT
),
126 DEFAULT_PINMUX(DAP3_SCLK_PP3
, I2S2
, NORMAL
, NORMAL
, INPUT
),
127 DEFAULT_PINMUX(PV2
, OWR
, NORMAL
, NORMAL
, OUTPUT
),
128 DEFAULT_PINMUX(PV3
, RSVD1
, NORMAL
, NORMAL
, OUTPUT
),
129 DEFAULT_PINMUX(CLK2_OUT_PW5
, EXTPERIPH2
, NORMAL
, NORMAL
, INPUT
),
130 DEFAULT_PINMUX(CLK2_REQ_PCC5
, DAP
, NORMAL
, NORMAL
, INPUT
),
131 DEFAULT_PINMUX(LCD_PWR1_PC1
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
132 DEFAULT_PINMUX(LCD_PWR2_PC6
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
133 DEFAULT_PINMUX(LCD_SDIN_PZ2
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
134 DEFAULT_PINMUX(LCD_SDOUT_PN5
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
135 DEFAULT_PINMUX(LCD_WR_N_PZ3
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
136 DEFAULT_PINMUX(LCD_CS0_N_PN4
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
137 DEFAULT_PINMUX(LCD_DC0_PN6
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
138 DEFAULT_PINMUX(LCD_SCK_PZ4
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
139 DEFAULT_PINMUX(LCD_PWR0_PB2
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
140 DEFAULT_PINMUX(LCD_PCLK_PB3
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
141 DEFAULT_PINMUX(LCD_DE_PJ1
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
142 DEFAULT_PINMUX(LCD_HSYNC_PJ3
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
143 DEFAULT_PINMUX(LCD_VSYNC_PJ4
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
144 DEFAULT_PINMUX(LCD_D0_PE0
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
145 DEFAULT_PINMUX(LCD_D1_PE1
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
146 DEFAULT_PINMUX(LCD_D2_PE2
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
147 DEFAULT_PINMUX(LCD_D3_PE3
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
148 DEFAULT_PINMUX(LCD_D4_PE4
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
149 DEFAULT_PINMUX(LCD_D5_PE5
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
150 DEFAULT_PINMUX(LCD_D6_PE6
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
151 DEFAULT_PINMUX(LCD_D7_PE7
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
152 DEFAULT_PINMUX(LCD_D8_PF0
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
153 DEFAULT_PINMUX(LCD_D9_PF1
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
154 DEFAULT_PINMUX(LCD_D10_PF2
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
155 DEFAULT_PINMUX(LCD_D11_PF3
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
156 DEFAULT_PINMUX(LCD_D12_PF4
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
157 DEFAULT_PINMUX(LCD_D13_PF5
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
158 DEFAULT_PINMUX(LCD_D14_PF6
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
159 DEFAULT_PINMUX(LCD_D15_PF7
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
160 DEFAULT_PINMUX(LCD_D16_PM0
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
161 DEFAULT_PINMUX(LCD_D17_PM1
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
162 DEFAULT_PINMUX(LCD_D18_PM2
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
163 DEFAULT_PINMUX(LCD_D19_PM3
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
164 DEFAULT_PINMUX(LCD_D20_PM4
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
165 DEFAULT_PINMUX(LCD_D21_PM5
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
166 DEFAULT_PINMUX(LCD_D22_PM6
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
167 DEFAULT_PINMUX(LCD_D23_PM7
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
168 DEFAULT_PINMUX(LCD_CS1_N_PW0
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
169 DEFAULT_PINMUX(LCD_M1_PW1
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
170 DEFAULT_PINMUX(LCD_DC1_PD2
, DISPLAYA
, NORMAL
, NORMAL
, INPUT
),
171 DEFAULT_PINMUX(CRT_HSYNC_PV6
, CRT
, NORMAL
, NORMAL
, OUTPUT
),
172 DEFAULT_PINMUX(CRT_VSYNC_PV7
, CRT
, NORMAL
, NORMAL
, OUTPUT
),
173 LV_PINMUX(VI_D0_PT4
, RSVD1
, NORMAL
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
174 LV_PINMUX(VI_D1_PD5
, SDMMC2
, NORMAL
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
175 LV_PINMUX(VI_D2_PL0
, SDMMC2
, NORMAL
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
176 LV_PINMUX(VI_D3_PL1
, SDMMC2
, NORMAL
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
177 LV_PINMUX(VI_D4_PL2
, VI
, NORMAL
, NORMAL
, OUTPUT
, DISABLE
, DISABLE
),
178 LV_PINMUX(VI_D5_PL3
, SDMMC2
, NORMAL
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
179 LV_PINMUX(VI_D7_PL5
, SDMMC2
, NORMAL
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
180 LV_PINMUX(VI_D10_PT2
, RSVD1
, NORMAL
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
181 LV_PINMUX(VI_MCLK_PT1
, VI
, UP
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
182 DEFAULT_PINMUX(UART2_RXD_PC3
, UARTB
, NORMAL
, NORMAL
, INPUT
),
183 DEFAULT_PINMUX(UART2_TXD_PC2
, UARTB
, NORMAL
, NORMAL
, OUTPUT
),
184 DEFAULT_PINMUX(UART2_RTS_N_PJ6
, UARTB
, NORMAL
, NORMAL
, OUTPUT
),
185 DEFAULT_PINMUX(UART2_CTS_N_PJ5
, UARTB
, NORMAL
, NORMAL
, INPUT
),
186 DEFAULT_PINMUX(UART3_TXD_PW6
, UARTC
, NORMAL
, NORMAL
, OUTPUT
),
187 DEFAULT_PINMUX(UART3_RXD_PW7
, UARTC
, NORMAL
, NORMAL
, INPUT
),
188 DEFAULT_PINMUX(UART3_CTS_N_PA1
, UARTC
, NORMAL
, NORMAL
, INPUT
),
189 DEFAULT_PINMUX(UART3_RTS_N_PC0
, UARTC
, NORMAL
, NORMAL
, OUTPUT
),
190 DEFAULT_PINMUX(PU0
, RSVD1
, NORMAL
, NORMAL
, INPUT
),
191 DEFAULT_PINMUX(PU1
, RSVD1
, NORMAL
, NORMAL
, OUTPUT
),
192 DEFAULT_PINMUX(PU2
, RSVD1
, NORMAL
, NORMAL
, INPUT
),
193 DEFAULT_PINMUX(PU3
, RSVD1
, NORMAL
, NORMAL
, INPUT
),
194 DEFAULT_PINMUX(PU4
, PWM1
, NORMAL
, NORMAL
, OUTPUT
),
195 DEFAULT_PINMUX(PU5
, PWM2
, NORMAL
, NORMAL
, OUTPUT
),
196 DEFAULT_PINMUX(PU6
, RSVD1
, NORMAL
, NORMAL
, INPUT
),
197 DEFAULT_PINMUX(DAP4_FS_PP4
, I2S3
, NORMAL
, NORMAL
, INPUT
),
198 DEFAULT_PINMUX(DAP4_DIN_PP5
, I2S3
, NORMAL
, NORMAL
, INPUT
),
199 DEFAULT_PINMUX(DAP4_DOUT_PP6
, I2S3
, NORMAL
, NORMAL
, INPUT
),
200 DEFAULT_PINMUX(DAP4_SCLK_PP7
, I2S3
, NORMAL
, NORMAL
, INPUT
),
201 DEFAULT_PINMUX(CLK3_OUT_PEE0
, EXTPERIPH3
, NORMAL
, NORMAL
, OUTPUT
),
202 DEFAULT_PINMUX(CLK3_REQ_PEE1
, DEV3
, NORMAL
, NORMAL
, INPUT
),
203 DEFAULT_PINMUX(GMI_WP_N_PC7
, GMI
, NORMAL
, NORMAL
, INPUT
),
204 DEFAULT_PINMUX(GMI_CS2_N_PK3
, RSVD1
, UP
, NORMAL
, INPUT
), /* EN_VDD_BL1 */
205 DEFAULT_PINMUX(GMI_AD8_PH0
, PWM0
, NORMAL
, NORMAL
, OUTPUT
), /* LCD1_BL_PWM */
206 DEFAULT_PINMUX(GMI_AD10_PH2
, NAND
, NORMAL
, NORMAL
, OUTPUT
), /* LCD1_BL_EN */
207 DEFAULT_PINMUX(GMI_A16_PJ7
, UARTD
, NORMAL
, NORMAL
, INPUT
),
208 DEFAULT_PINMUX(GMI_A17_PB0
, UARTD
, NORMAL
, NORMAL
, INPUT
),
209 DEFAULT_PINMUX(GMI_A18_PB1
, UARTD
, NORMAL
, NORMAL
, INPUT
),
210 DEFAULT_PINMUX(GMI_A19_PK7
, UARTD
, NORMAL
, NORMAL
, INPUT
),
213 /* Multiplexed with KB_ROW10/KB_ROW11/KB_ROW12/KB_ROW15 */
214 DEFAULT_PINMUX(CAM_MCLK_PCC0
, VI_ALT2
, UP
, TRISTATE
, INPUT
),
215 DEFAULT_PINMUX(PCC1
, RSVD1
, NORMAL
, TRISTATE
, INPUT
),
216 DEFAULT_PINMUX(PBB0
, RSVD1
, NORMAL
, TRISTATE
, INPUT
),
217 DEFAULT_PINMUX(PBB3
, VGP3
, NORMAL
, TRISTATE
, INPUT
),
219 DEFAULT_PINMUX(PBB5
, VGP5
, NORMAL
, NORMAL
, INPUT
),
220 DEFAULT_PINMUX(PBB6
, VGP6
, NORMAL
, NORMAL
, INPUT
),
221 DEFAULT_PINMUX(PBB7
, I2S4
, NORMAL
, NORMAL
, INPUT
),
222 DEFAULT_PINMUX(PCC2
, I2S4
, NORMAL
, NORMAL
, INPUT
),
223 DEFAULT_PINMUX(JTAG_RTCK_PU7
, RTCK
, NORMAL
, NORMAL
, OUTPUT
),
226 DEFAULT_PINMUX(KB_ROW0_PR0
, RSVD2
, NORMAL
, TRISTATE
, INPUT
),
227 DEFAULT_PINMUX(KB_ROW1_PR1
, RSVD2
, NORMAL
, TRISTATE
, INPUT
),
228 DEFAULT_PINMUX(KB_ROW2_PR2
, RSVD2
, NORMAL
, TRISTATE
, INPUT
),
229 DEFAULT_PINMUX(KB_ROW3_PR3
, RSVD2
, NORMAL
, TRISTATE
, INPUT
),
230 DEFAULT_PINMUX(KB_ROW4_PR4
, RSVD3
, NORMAL
, TRISTATE
, INPUT
),
231 DEFAULT_PINMUX(KB_ROW5_PR5
, KBC
, NORMAL
, TRISTATE
, INPUT
),
232 DEFAULT_PINMUX(KB_ROW6_PR6
, KBC
, NORMAL
, TRISTATE
, INPUT
),
233 DEFAULT_PINMUX(KB_ROW7_PR7
, KBC
, NORMAL
, TRISTATE
, INPUT
),
234 DEFAULT_PINMUX(KB_ROW8_PS0
, KBC
, NORMAL
, TRISTATE
, INPUT
),
235 DEFAULT_PINMUX(KB_ROW9_PS1
, KBC
, NORMAL
, TRISTATE
, INPUT
),
238 DEFAULT_PINMUX(KB_ROW10_PS2
, SDMMC2
, NORMAL
, NORMAL
, INPUT
),
239 DEFAULT_PINMUX(KB_ROW11_PS3
, SDMMC2
, UP
, NORMAL
, INPUT
),
240 DEFAULT_PINMUX(KB_ROW12_PS4
, SDMMC2
, UP
, NORMAL
, INPUT
),
241 DEFAULT_PINMUX(KB_ROW13_PS5
, SDMMC2
, UP
, NORMAL
, INPUT
),
242 DEFAULT_PINMUX(KB_ROW14_PS6
, SDMMC2
, UP
, NORMAL
, INPUT
),
243 DEFAULT_PINMUX(KB_ROW15_PS7
, SDMMC2
, UP
, NORMAL
, INPUT
),
245 DEFAULT_PINMUX(KB_COL0_PQ0
, KBC
, UP
, NORMAL
, INPUT
),
246 DEFAULT_PINMUX(KB_COL1_PQ1
, KBC
, UP
, NORMAL
, INPUT
),
247 DEFAULT_PINMUX(KB_COL2_PQ2
, KBC
, UP
, NORMAL
, INPUT
),
248 DEFAULT_PINMUX(KB_COL3_PQ3
, KBC
, UP
, NORMAL
, INPUT
),
249 DEFAULT_PINMUX(KB_COL4_PQ4
, KBC
, UP
, NORMAL
, INPUT
),
250 DEFAULT_PINMUX(KB_COL5_PQ5
, KBC
, UP
, NORMAL
, INPUT
),
251 DEFAULT_PINMUX(KB_COL6_PQ6
, KBC
, UP
, NORMAL
, INPUT
),
252 DEFAULT_PINMUX(KB_COL7_PQ7
, KBC
, UP
, NORMAL
, INPUT
),
253 DEFAULT_PINMUX(PV0
, RSVD1
, UP
, NORMAL
, INPUT
),
255 DEFAULT_PINMUX(CLK_32K_OUT_PA0
, BLINK
, NORMAL
, NORMAL
, OUTPUT
),
256 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5
, SYSCLK
, NORMAL
, NORMAL
, OUTPUT
),
257 DEFAULT_PINMUX(OWR
, OWR
, NORMAL
, NORMAL
, INPUT
),
258 DEFAULT_PINMUX(DAP1_FS_PN0
, I2S0
, NORMAL
, NORMAL
, INPUT
),
259 DEFAULT_PINMUX(DAP1_DIN_PN1
, I2S0
, NORMAL
, NORMAL
, INPUT
),
260 DEFAULT_PINMUX(DAP1_DOUT_PN2
, I2S0
, NORMAL
, NORMAL
, INPUT
),
261 DEFAULT_PINMUX(DAP1_SCLK_PN3
, I2S0
, NORMAL
, NORMAL
, INPUT
),
262 DEFAULT_PINMUX(CLK1_REQ_PEE2
, DAP
, NORMAL
, NORMAL
, INPUT
),
263 DEFAULT_PINMUX(CLK1_OUT_PW4
, EXTPERIPH1
, NORMAL
, NORMAL
, INPUT
),
264 DEFAULT_PINMUX(SPDIF_IN_PK6
, SPDIF
, NORMAL
, NORMAL
, INPUT
),
265 DEFAULT_PINMUX(SPDIF_OUT_PK5
, SPDIF
, NORMAL
, NORMAL
, OUTPUT
),
266 DEFAULT_PINMUX(DAP2_FS_PA2
, I2S1
, NORMAL
, NORMAL
, INPUT
),
267 DEFAULT_PINMUX(DAP2_DIN_PA4
, I2S1
, NORMAL
, NORMAL
, INPUT
),
268 DEFAULT_PINMUX(DAP2_DOUT_PA5
, I2S1
, NORMAL
, NORMAL
, INPUT
),
269 DEFAULT_PINMUX(DAP2_SCLK_PA3
, I2S1
, NORMAL
, NORMAL
, INPUT
),
271 DEFAULT_PINMUX(SPI2_CS1_N_PW2
, SPI2
, UP
, NORMAL
, INPUT
),
272 DEFAULT_PINMUX(SPI1_MOSI_PX4
, SPI1
, NORMAL
, NORMAL
, INPUT
),
273 DEFAULT_PINMUX(SPI1_SCK_PX5
, SPI1
, NORMAL
, NORMAL
, INPUT
),
274 DEFAULT_PINMUX(SPI1_CS0_N_PX6
, SPI1
, NORMAL
, NORMAL
, INPUT
),
275 DEFAULT_PINMUX(SPI1_MISO_PX7
, SPI1
, NORMAL
, NORMAL
, INPUT
),
278 DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0
, RSVD2
, NORMAL
, NORMAL
, OUTPUT
),
280 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1
, PCIE
, NORMAL
, NORMAL
, OUTPUT
),
283 DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2
, RSVD2
, NORMAL
, NORMAL
, OUTPUT
),
285 DEFAULT_PINMUX(PEX_WAKE_N_PDD3
, PCIE
, NORMAL
, NORMAL
, INPUT
),
286 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4
, PCIE
, NORMAL
, NORMAL
, INPUT
),
287 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5
, PCIE
, NORMAL
, NORMAL
, OUTPUT
),
288 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6
, PCIE
, NORMAL
, NORMAL
, INPUT
),
289 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7
, PCIE
, NORMAL
, NORMAL
, INPUT
),
290 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6
, PCIE
, NORMAL
, NORMAL
, OUTPUT
),
291 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7
, PCIE
, NORMAL
, NORMAL
, INPUT
),
292 DEFAULT_PINMUX(HDMI_CEC_PEE3
, CEC
, NORMAL
, NORMAL
, INPUT
),
293 DEFAULT_PINMUX(HDMI_INT_PN7
, RSVD1
, NORMAL
, TRISTATE
, INPUT
),
297 DEFAULT_PINMUX(GMI_IORDY_PI5
, RSVD1
, UP
, NORMAL
, INPUT
),
299 LV_PINMUX(VI_D11_PT3
, RSVD1
, UP
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
301 /* Touch panel GPIO */
303 DEFAULT_PINMUX(GMI_AD12_PH4
, NAND
, UP
, NORMAL
, INPUT
),
306 DEFAULT_PINMUX(GMI_AD14_PH6
, NAND
, NORMAL
, NORMAL
, OUTPUT
),
308 /* Power rails GPIO */
309 DEFAULT_PINMUX(SPI2_SCK_PX2
, GMI
, NORMAL
, NORMAL
, INPUT
),
310 DEFAULT_PINMUX(PBB4
, VGP4
, NORMAL
, NORMAL
, INPUT
),
311 DEFAULT_PINMUX(KB_ROW8_PS0
, KBC
, UP
, NORMAL
, INPUT
),
312 DEFAULT_PINMUX(SDMMC3_DAT5_PD0
, SDMMC3
, UP
, NORMAL
, INPUT
),
313 DEFAULT_PINMUX(SDMMC3_DAT4_PD1
, SDMMC3
, UP
, NORMAL
, INPUT
),
315 LV_PINMUX(VI_D6_PL4
, VI
, NORMAL
, NORMAL
, OUTPUT
, DISABLE
, DISABLE
),
316 LV_PINMUX(VI_D8_PL6
, VI
, NORMAL
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
317 LV_PINMUX(VI_D9_PL7
, VI
, NORMAL
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
318 LV_PINMUX(VI_PCLK_PT0
, RSVD1
, UP
, TRISTATE
, INPUT
, DISABLE
, DISABLE
),
319 LV_PINMUX(VI_HSYNC_PD7
, RSVD1
, NORMAL
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
320 LV_PINMUX(VI_VSYNC_PD6
, RSVD1
, NORMAL
, NORMAL
, INPUT
, DISABLE
, DISABLE
),
323 static struct pmux_pingrp_config unused_pins_lowpower
[] = {
324 DEFAULT_PINMUX(GMI_WAIT_PI7
, NAND
, UP
, TRISTATE
, OUTPUT
),
325 DEFAULT_PINMUX(GMI_ADV_N_PK0
, NAND
, NORMAL
, TRISTATE
, OUTPUT
),
326 DEFAULT_PINMUX(GMI_CLK_PK1
, NAND
, NORMAL
, TRISTATE
, OUTPUT
),
327 DEFAULT_PINMUX(GMI_CS3_N_PK4
, NAND
, NORMAL
, NORMAL
, OUTPUT
),
328 DEFAULT_PINMUX(GMI_CS7_N_PI6
, NAND
, UP
, NORMAL
, INPUT
),
329 DEFAULT_PINMUX(GMI_AD0_PG0
, NAND
, NORMAL
, TRISTATE
, OUTPUT
),
330 DEFAULT_PINMUX(GMI_AD1_PG1
, NAND
, NORMAL
, TRISTATE
, OUTPUT
),
331 DEFAULT_PINMUX(GMI_AD2_PG2
, NAND
, NORMAL
, TRISTATE
, OUTPUT
),
332 DEFAULT_PINMUX(GMI_AD3_PG3
, NAND
, NORMAL
, TRISTATE
, OUTPUT
),
333 DEFAULT_PINMUX(GMI_AD4_PG4
, NAND
, NORMAL
, TRISTATE
, OUTPUT
),
334 DEFAULT_PINMUX(GMI_AD5_PG5
, NAND
, NORMAL
, TRISTATE
, OUTPUT
),
335 DEFAULT_PINMUX(GMI_AD6_PG6
, NAND
, NORMAL
, TRISTATE
, OUTPUT
),
336 DEFAULT_PINMUX(GMI_AD7_PG7
, NAND
, NORMAL
, TRISTATE
, OUTPUT
),
337 DEFAULT_PINMUX(GMI_AD9_PH1
, PWM1
, NORMAL
, NORMAL
, OUTPUT
),
338 DEFAULT_PINMUX(GMI_AD11_PH3
, NAND
, NORMAL
, NORMAL
, OUTPUT
),
339 DEFAULT_PINMUX(GMI_AD13_PH5
, NAND
, UP
, NORMAL
, INPUT
),
340 DEFAULT_PINMUX(GMI_WR_N_PI0
, NAND
, NORMAL
, TRISTATE
, OUTPUT
),
341 DEFAULT_PINMUX(GMI_OE_N_PI1
, NAND
, NORMAL
, TRISTATE
, OUTPUT
),
342 DEFAULT_PINMUX(GMI_DQS_PI2
, NAND
, NORMAL
, TRISTATE
, OUTPUT
),
345 static struct pmux_drvgrp_config colibri_t30_padctrl
[] = {
346 /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
347 DEFAULT_PADCFG(SDIO1
, SDIOCFG_DRVUP_SLWF
, SDIOCFG_DRVDN_SLWR
, \
348 SDIOCFG_DRVUP
, SDIOCFG_DRVDN
, NONE
, DISABLE
, DISABLE
),
350 #endif /* _PINMUX_CONFIG_COLIBRI_T30_H_ */