board/tqc/tqm5200/mt48lc16m16a2-75.h

   1 /*
   2  * (C) Copyright 2004
   3  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #define SDRAM_DDR       0               /* is SDR */
   9
  10 /* Settings for XLB = 132 MHz */
  11 #define SDRAM_MODE      0x00CD0000
  12 /* #define SDRAM_MODE   0x008D0000 */ /* CAS latency 2 */
  13 #define SDRAM_CONTROL   0x504F0000
  14 #define SDRAM_CONFIG1   0xD2322800
  15 /* #define SDRAM_CONFIG1        0xD2222800 */ /* CAS latency 2 */
  16 /*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */
  17 #define SDRAM_CONFIG2   0x8AD70000
  18 /*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */