3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 /* UPM pattern for bus clock = 66.7 MHz */
31 static const uint upmTable67
[] =
33 /* Offset UPM Read Single RAM array entry -> NAND Read Data */
34 /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
35 /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
37 /* UPM Read Burst RAM array entry -> unused */
38 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
39 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
41 /* UPM Read Burst RAM array entry -> unused */
42 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
43 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
45 /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
46 /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
47 /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
49 /* UPM Write Burst RAM array entry -> unused */
50 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
51 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
52 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
53 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
55 /* UPM Refresh Timer RAM array entry -> unused */
56 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
57 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
58 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
60 /* UPM Exception RAM array entry -> unsused */
61 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
64 /* UPM pattern for bus clock = 100 MHz */
65 static const uint upmTable100
[] =
67 /* Offset UPM Read Single RAM array entry -> NAND Read Data */
68 /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
69 /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
71 /* UPM Read Burst RAM array entry -> unused */
72 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
73 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
75 /* UPM Read Burst RAM array entry -> unused */
76 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
77 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
79 /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
80 /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
81 /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
83 /* UPM Write Burst RAM array entry -> unused */
84 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
85 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
86 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
87 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
89 /* UPM Refresh Timer RAM array entry -> unused */
90 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
91 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
92 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
94 /* UPM Exception RAM array entry -> unsused */
95 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
98 /* UPM pattern for bus clock = 133.3 MHz */
99 static const uint upmTable133
[] =
101 /* Offset UPM Read Single RAM array entry -> NAND Read Data */
102 /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
103 /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
105 /* UPM Read Burst RAM array entry -> unused */
106 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
107 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
109 /* UPM Read Burst RAM array entry -> unused */
110 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
111 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
113 /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
114 /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
115 /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
117 /* UPM Write Burst RAM array entry -> unused */
118 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
119 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
120 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
121 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
123 /* UPM Refresh Timer RAM array entry -> unused */
124 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
125 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
126 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
128 /* UPM Exception RAM array entry -> unsused */
129 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
132 static int chipsel
= 0;
134 #if defined(CONFIG_CMD_NAND)
137 #include <linux/mtd/mtd.h>
141 static void upmnand_write_byte(struct mtd_info
*mtdinfo
, u_char byte
)
143 struct nand_chip
*this = mtdinfo
->priv
;
144 ulong base
= (ulong
) (this->IO_ADDR_W
+ chipsel
* CONFIG_SYS_NAND_CS_DIST
);
147 WRITE_NAND_UPM(byte
, base
, CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS
);
148 } else if (hwctl
& 0x2) {
149 WRITE_NAND_UPM(byte
, base
, CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS
);
151 WRITE_NAND(byte
, base
);
155 static void upmnand_hwcontrol(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
157 if (ctrl
& NAND_CTRL_CHANGE
) {
158 if ( ctrl
& NAND_CLE
)
162 if ( ctrl
& NAND_ALE
)
167 if (cmd
!= NAND_CMD_NONE
)
168 upmnand_write_byte (mtd
, cmd
);
171 static u_char
upmnand_read_byte(struct mtd_info
*mtdinfo
)
173 struct nand_chip
*this = mtdinfo
->priv
;
174 ulong base
= (ulong
) (this->IO_ADDR_W
+ chipsel
* CONFIG_SYS_NAND_CS_DIST
);
176 return READ_NAND(base
);
179 static int tqm8272_dev_ready(struct mtd_info
*mtdinfo
)
181 /* constant delay (see also tR in the datasheet) */
186 #ifndef CONFIG_NAND_SPL
187 static void tqm8272_read_buf(struct mtd_info
*mtdinfo
, uint8_t *buf
, int len
)
189 struct nand_chip
*this = mtdinfo
->priv
;
190 unsigned char *base
= (unsigned char *) (this->IO_ADDR_W
+ chipsel
* CONFIG_SYS_NAND_CS_DIST
);
193 for (i
= 0; i
< len
; i
++)
197 static void tqm8272_write_buf(struct mtd_info
*mtdinfo
, const uint8_t *buf
, int len
)
199 struct nand_chip
*this = mtdinfo
->priv
;
200 unsigned char *base
= (unsigned char *) (this->IO_ADDR_W
+ chipsel
* CONFIG_SYS_NAND_CS_DIST
);
203 for (i
= 0; i
< len
; i
++)
207 static int tqm8272_verify_buf(struct mtd_info
*mtdinfo
, const uint8_t *buf
, int len
)
209 struct nand_chip
*this = mtdinfo
->priv
;
210 unsigned char *base
= (unsigned char *) (this->IO_ADDR_W
+ chipsel
* CONFIG_SYS_NAND_CS_DIST
);
213 for (i
= 0; i
< len
; i
++)
218 #endif /* #ifndef CONFIG_NAND_SPL */
220 void board_nand_select_device(struct nand_chip
*nand
, int chip
)
225 int board_nand_init(struct nand_chip
*nand
)
227 static int UpmInit
= 0;
228 volatile immap_t
* immr
= (immap_t
*)CONFIG_SYS_IMMR
;
229 volatile memctl8260_t
*memctl
= &immr
->im_memctl
;
231 if (hwinf
.nand
== 0) return -1;
235 switch (hwinf
.busclk_real
) {
237 upmconfig (UPMB
, (uint
*) upmTable100
,
238 sizeof (upmTable100
) / sizeof (uint
));
241 upmconfig (UPMB
, (uint
*) upmTable133
,
242 sizeof (upmTable133
) / sizeof (uint
));
245 upmconfig (UPMB
, (uint
*) upmTable67
,
246 sizeof (upmTable67
) / sizeof (uint
));
252 /* Setup the memctrl */
253 memctl
->memc_or3
= CONFIG_SYS_NAND_OR
;
254 memctl
->memc_br3
= CONFIG_SYS_NAND_BR
;
255 memctl
->memc_mbmr
= (MxMR_OP_NORM
);
257 nand
->ecc
.mode
= NAND_ECC_SOFT
;
259 nand
->cmd_ctrl
= upmnand_hwcontrol
;
260 nand
->read_byte
= upmnand_read_byte
;
261 nand
->dev_ready
= tqm8272_dev_ready
;
263 #ifndef CONFIG_NAND_SPL
264 nand
->write_buf
= tqm8272_write_buf
;
265 nand
->read_buf
= tqm8272_read_buf
;
266 nand
->verify_buf
= tqm8272_verify_buf
;
270 * Select required NAND chip
272 board_nand_select_device(nand
, 0);