3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/m8260_pci.h>
37 #define deb_printf(fmt,arg...) \
38 printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg)
40 #define deb_printf(fmt,arg...) \
44 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
45 unsigned long board_get_cpu_clk_f (void);
49 * I/O Port configuration table
51 * if conf is 1, then that port pin will be configured at boot time
52 * according to the five values podr/pdir/ppar/psor/pdat for that entry
55 const iop_conf_t iop_conf_tab
[4][32] = {
57 /* Port A configuration */
58 { /* conf ppar psor pdir podr pdat */
59 /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */
60 /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */
61 /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */
62 /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */
63 /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */
64 /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */
65 /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
66 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
67 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
68 /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
69 /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
70 /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
71 /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
72 /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
73 /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */
74 /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */
75 /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */
76 /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */
77 /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */
78 /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */
79 /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */
80 /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */
81 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
82 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
83 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
84 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
85 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
86 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
87 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
88 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
89 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
90 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
93 /* Port B configuration */
94 { /* conf ppar psor pdir podr pdat */
95 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
96 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
97 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
98 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
99 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
100 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
101 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
102 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
103 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
104 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
105 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
106 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
107 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
108 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
109 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
110 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
111 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
112 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
113 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
114 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
115 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
116 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
117 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
118 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
119 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
120 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
121 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
122 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
123 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
124 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
125 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
126 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
130 { /* conf ppar psor pdir podr pdat */
131 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
132 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
133 /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
134 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
135 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
136 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
137 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
138 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
139 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
140 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
141 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
142 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
143 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
144 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
145 /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */
146 /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/
147 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
148 /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
149 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
150 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
151 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
152 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */
153 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */
154 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
155 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
156 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
157 /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */
158 /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */
159 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
160 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
161 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
162 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
166 { /* conf ppar psor pdir podr pdat */
167 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
168 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
169 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
170 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
171 /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
172 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
173 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
174 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
175 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
176 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
177 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
178 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
179 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
180 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
181 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
182 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
183 #if defined(CONFIG_SOFT_I2C)
184 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
185 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
187 #if defined(CONFIG_HARD_I2C)
188 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
189 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
190 #else /* normal I/O port pins */
191 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
192 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
195 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
196 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
197 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
198 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
199 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
200 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
201 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
202 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
203 /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */
204 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
205 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
206 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
207 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
208 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
212 /* UPM pattern for slow init */
213 static const uint upmTableSlow
[] =
215 /* Offset UPM Read Single RAM array entry */
216 /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00,
217 /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07,
219 /* UPM Read Burst RAM array entry -> unused */
220 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
221 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
223 /* UPM Read Burst RAM array entry -> unused */
224 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
225 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
227 /* UPM Write Single RAM array entry */
228 /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80,
229 /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
231 /* UPM Write Burst RAM array entry -> unused */
232 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
233 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
234 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
235 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
237 /* UPM Refresh Timer RAM array entry -> unused */
238 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
239 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
240 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
242 /* UPM Exception RAM array entry -> unused */
243 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
246 /* UPM pattern for fast init */
247 static const uint upmTableFast
[] =
249 /* Offset UPM Read Single RAM array entry */
250 /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00,
251 /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07,
253 /* UPM Read Burst RAM array entry -> unused */
254 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
255 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
257 /* UPM Read Burst RAM array entry -> unused */
258 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
259 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
261 /* UPM Write Single RAM array entry */
262 /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00,
263 /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
265 /* UPM Write Burst RAM array entry -> unused */
266 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
267 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
268 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
269 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
271 /* UPM Refresh Timer RAM array entry -> unused */
272 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
273 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
274 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
276 /* UPM Exception RAM array entry -> unused */
277 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
281 /* ------------------------------------------------------------------------- */
283 /* Check Board Identity:
285 int checkboard (void)
287 char *p
= (char *) HWIB_INFO_START_ADDR
;
290 if (*((unsigned long *)p
) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC
) {
293 puts ("No HWIB assuming TQM8272");
300 /* ------------------------------------------------------------------------- */
301 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
302 static int get_cas_latency (void)
304 /* get it from the option -ts in CIB */
308 char *p
= (char *) CIB_INFO_START_ADDR
;
310 while ((*p
!= '\0') && (pos
< CIB_INFO_LEN
)) {
311 if (*p
< ' ' || *p
> '~') { /* ASCII strings! */
315 if ((p
[1] == 't') && (p
[2] == 's')) {
326 static ulong
set_sdram_timing (volatile uint
*sdmr_ptr
, ulong sdmr
, int col
)
328 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
329 int clk
= board_get_cpu_clk_f ();
330 volatile immap_t
*immr
= (immap_t
*)CONFIG_SYS_IMMR
;
331 int busmode
= (immr
->im_siu_conf
.sc_bcr
& BCR_EBM
? 1 : 0);
334 sdmr
= sdmr
& ~(PSDMR_RFRC_MSK
| PSDMR_PRETOACT_MSK
| PSDMR_WRC_MSK
| \
339 sdmr
|= (PSDMR_RFRC_66MHZ_60X
| \
340 PSDMR_PRETOACT_66MHZ_60X
| \
341 PSDMR_WRC_66MHZ_60X
| \
342 PSDMR_BUFCMD_66MHZ_60X
);
345 sdmr
|= (PSDMR_RFRC_100MHZ_60X
| \
346 PSDMR_PRETOACT_100MHZ_60X
| \
347 PSDMR_WRC_100MHZ_60X
| \
348 PSDMR_BUFCMD_100MHZ_60X
);
355 sdmr
|= (PSDMR_RFRC_66MHZ_SINGLE
| \
356 PSDMR_PRETOACT_66MHZ_SINGLE
| \
357 PSDMR_WRC_66MHZ_SINGLE
| \
358 PSDMR_BUFCMD_66MHZ_SINGLE
);
361 sdmr
|= (PSDMR_RFRC_100MHZ_SINGLE
| \
362 PSDMR_PRETOACT_100MHZ_SINGLE
| \
363 PSDMR_WRC_100MHZ_SINGLE
| \
364 PSDMR_BUFCMD_100MHZ_SINGLE
);
367 sdmr
|= (PSDMR_RFRC_133MHZ_SINGLE
| \
368 PSDMR_PRETOACT_133MHZ_SINGLE
| \
369 PSDMR_WRC_133MHZ_SINGLE
| \
370 PSDMR_BUFCMD_133MHZ_SINGLE
);
374 cas
= get_cas_latency();
375 sdmr
&=~ (PSDMR_CL_MSK
| PSDMR_LDOTOPRE_MSK
);
377 sdmr
|= ((cas
- 1) << 6);
384 /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
386 * This routine performs standard 8260 initialization sequence
387 * and calculates the available memory size. It may be called
388 * several times to try different SDRAM configurations on both
389 * 60x and local buses.
391 static long int try_init (volatile memctl8260_t
* memctl
, ulong sdmr
,
392 ulong orx
, volatile uchar
* base
, int col
)
394 volatile uchar c
= 0xff;
395 volatile uint
*sdmr_ptr
;
396 volatile uint
*orx_ptr
;
400 /* We must be able to test a location outsize the maximum legal size
401 * to find out THAT we are outside; but this address still has to be
402 * mapped by the controller. That means, that the initial mapping has
403 * to be (at least) twice as large as the maximum expected size.
405 maxsize
= (1 + (~orx
| 0x7fff)) / 2;
407 /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
408 * we are configuring CS1 if base != 0
410 sdmr_ptr
= base
? &memctl
->memc_lsdmr
: &memctl
->memc_psdmr
;
411 orx_ptr
= base
? &memctl
->memc_or2
: &memctl
->memc_or1
;
414 sdmr
= set_sdram_timing (sdmr_ptr
, sdmr
, col
);
416 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
418 * "At system reset, initialization software must set up the
419 * programmable parameters in the memory controller banks registers
420 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
421 * system software should execute the following initialization sequence
422 * for each SDRAM device.
424 * 1. Issue a PRECHARGE-ALL-BANKS command
425 * 2. Issue eight CBR REFRESH commands
426 * 3. Issue a MODE-SET command to initialize the mode register
428 * The initial commands are executed by setting P/LSDMR[OP] and
429 * accessing the SDRAM with a single-byte transaction."
431 * The appropriate BRx/ORx registers have already been set when we
432 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
435 *sdmr_ptr
= sdmr
| PSDMR_OP_PREA
;
438 *sdmr_ptr
= sdmr
| PSDMR_OP_CBRR
;
439 for (i
= 0; i
< 8; i
++)
442 *sdmr_ptr
= sdmr
| PSDMR_OP_MRW
;
443 *(base
+ CONFIG_SYS_MRS_OFFS
) = c
; /* setting MR on address lines */
445 *sdmr_ptr
= sdmr
| PSDMR_OP_NORM
| PSDMR_RFEN
;
448 size
= get_ram_size((long *)base
, maxsize
);
449 *orx_ptr
= orx
| ~(size
- 1);
454 phys_size_t
initdram (int board_type
)
456 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
457 volatile memctl8260_t
*memctl
= &immap
->im_memctl
;
459 #ifndef CONFIG_SYS_RAMBOOT
464 psize
= 16 * 1024 * 1024;
467 memctl
->memc_psrt
= CONFIG_SYS_PSRT
;
468 memctl
->memc_mptpr
= CONFIG_SYS_MPTPR
;
470 #ifndef CONFIG_SYS_RAMBOOT
473 size8
= try_init (memctl
, CONFIG_SYS_PSDMR_8COL
, CONFIG_SYS_OR1_8COL
,
474 (uchar
*) CONFIG_SYS_SDRAM_BASE
, 8);
475 size9
= try_init (memctl
, CONFIG_SYS_PSDMR_9COL
, CONFIG_SYS_OR1_9COL
,
476 (uchar
*) CONFIG_SYS_SDRAM_BASE
, 9);
480 printf ("(60x:9COL - %ld MB, ", psize
>> 20);
482 psize
= try_init (memctl
, CONFIG_SYS_PSDMR_8COL
, CONFIG_SYS_OR1_8COL
,
483 (uchar
*) CONFIG_SYS_SDRAM_BASE
, 8);
484 printf ("(60x:8COL - %ld MB, ", psize
>> 20);
487 #endif /* CONFIG_SYS_RAMBOOT */
495 static inline int scanChar (char *p
, int len
, unsigned long *number
)
501 if ((*p
>= '0') && (*p
<= '9')) {
506 if (*p
== '-') return akt
;
514 static int dump_hwib(void)
516 HWIB_INFO
*hw
= &hwinf
;
517 volatile immap_t
*immr
= (immap_t
*)CONFIG_SYS_IMMR
;
518 char *s
= getenv("serial#");
521 printf ("HWIB on %x\n", HWIB_INFO_START_ADDR
);
522 printf ("serial : %s\n", s
);
523 printf ("ethaddr: %s\n", hw
->ethaddr
);
524 printf ("FLASH : %x nr:%d\n", hw
->flash
, hw
->flash_nr
);
525 printf ("RAM : %x cs:%d\n", hw
->ram
, hw
->ram_cs
);
526 printf ("CPU : %lu\n", hw
->cpunr
);
527 printf ("CAN : %d\n", hw
->can
);
528 if (hw
->eeprom
) printf ("EEprom : %x\n", hw
->eeprom
);
529 else printf ("No EEprom\n");
531 printf ("NAND : %x\n", hw
->nand
);
532 printf ("NAND CS: %d\n", hw
->nand_cs
);
533 } else { printf ("No NAND\n");}
534 printf ("Bus %s mode.\n", (hw
->Bus
? "60x" : "Single PQII"));
535 printf (" real : %s\n", (immr
->im_siu_conf
.sc_bcr
& BCR_EBM
? \
536 "60x" : "Single PQII"));
537 printf ("Option : %lx\n", hw
->option
);
538 printf ("%s Security Engine\n", (hw
->SecEng
? "with" : "no"));
539 printf ("CPM Clk: %d\n", hw
->cpmcl
);
540 printf ("CPU Clk: %d\n", hw
->cpucl
);
541 printf ("Bus Clk: %d\n", hw
->buscl
);
542 if (hw
->busclk_real_ok
) {
543 printf (" real Clk: %d\n", hw
->busclk_real
);
545 printf ("CAS : %d\n", get_cas_latency());
547 printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR
);
552 static inline int search_real_busclk (int *clk
)
554 int part
= 0, pos
= 0;
555 char *p
= (char *) CIB_INFO_START_ADDR
;
558 while ((*p
!= '\0') && (pos
< CIB_INFO_LEN
)) {
559 if (*p
< ' ' || *p
> '~') { /* ASCII strings! */
601 int analyse_hwib (void)
603 char *p
= (char *) HWIB_INFO_START_ADDR
;
605 int part
= 1, i
= 0, pos
= 0;
606 HWIB_INFO
*hw
= &hwinf
;
608 deb_printf(" %s pointer: %p\n", __FUNCTION__
, p
);
610 if (*((unsigned long *)p
) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC
) {
611 deb_printf("No HWIB\n");
615 if (scanChar (p
, 4, &hw
->cpunr
) < 0) {
616 deb_printf("No CPU\n");
621 hw
->flash
= 0x200000 << (*p
- 'A');
623 hw
->flash_nr
= *p
- '0';
626 hw
->ram
= 0x2000000 << (*p
- 'A');
633 if (*p
== 'A') hw
->can
= 1;
634 if (*p
== 'B') hw
->can
= 2;
636 p
+=1; /* connector */
638 hw
->eeprom
= 0x1000 << (*p
- 'A');
642 if ((*p
< '0') || (*p
> '9')) {
643 /* NAND before z-option */
644 hw
->nand
= 0x8000000 << (*p
- 'A');
646 hw
->nand_cs
= *p
- '0';
650 anz
= scanChar (p
, 4, &hw
->option
);
652 deb_printf("No option\n");
655 if (hw
->option
& 0x8) hw
->Bus
= 1;
658 deb_printf("No -\n");
668 case 'M': hw
->cpucl
= 266666666;
670 case 'P': hw
->cpucl
= 300000000;
672 case 'T': hw
->cpucl
= 400000000;
675 deb_printf("No CPU Clk: %c\n", *p
);
681 case 'I': hw
->cpmcl
= 200000000;
683 case 'M': hw
->cpmcl
= 300000000;
686 deb_printf("No CPM Clk\n");
692 case 'B': hw
->buscl
= 66666666;
694 case 'E': hw
->buscl
= 100000000;
696 case 'F': hw
->buscl
= 133333333;
699 deb_printf("No BUS Clk\n");
706 /* search MAC Address */
707 while ((*p
!= '\0') && (pos
< CONFIG_SYS_HWINFO_SIZE
)) {
708 if (*p
< ' ' || *p
> '~') { /* ASCII strings! */
718 case 3: /* Copy MAC address */
724 hw
->ethaddr
[i
++] = *p
;
726 hw
->ethaddr
[i
++] = ':';
733 hw
->busclk_real_ok
= search_real_busclk (&hw
->busclk_real
);
737 #if defined(CONFIG_GET_CPU_STR_F)
738 /* !! This routine runs from Flash */
739 char get_cpu_str_f (char *buf
)
741 char *p
= (char *) HWIB_INFO_START_ADDR
;
747 if (*((unsigned long *)p
) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC
) {
763 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
764 /* !! This routine runs from Flash */
765 unsigned long board_get_cpu_clk_f (void)
767 char *p
= (char *) HWIB_INFO_START_ADDR
;
770 if (*((unsigned long *)p
) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC
) {
771 if (search_real_busclk (&i
))
774 return CONFIG_8260_CLKIN
;
778 #if CONFIG_BOARD_EARLY_INIT_R
780 static int can_test (unsigned long off
)
782 volatile unsigned char *base
= (unsigned char *) (CONFIG_SYS_CAN_BASE
+ off
);
784 *(base
+ 0x17) = 'T';
785 *(base
+ 0x18) = 'Q';
786 *(base
+ 0x19) = 'M';
787 if ((*(base
+ 0x17) != 'T') ||
788 (*(base
+ 0x18) != 'Q') ||
789 (*(base
+ 0x19) != 'M')) {
795 static int can_config_one (unsigned long off
)
797 volatile unsigned char *ctrl
= (unsigned char *) (CONFIG_SYS_CAN_BASE
+ off
);
798 volatile unsigned char *cpu_if
= (unsigned char *) (CONFIG_SYS_CAN_BASE
+ off
+ 0x02);
799 volatile unsigned char *clkout
= (unsigned char *) (CONFIG_SYS_CAN_BASE
+ off
+ 0x1f);
813 static int can_config (void)
817 if (hwinf
.can
== 2) {
818 can_config_one (0x100);
820 /* make Test if they really there */
822 ret
+= can_test (0x100);
826 static int init_can (void)
828 volatile immap_t
* immr
= (immap_t
*)CONFIG_SYS_IMMR
;
829 volatile memctl8260_t
*memctl
= &immr
->im_memctl
;
832 if ((hwinf
.OK
) && (hwinf
.can
)) {
833 memctl
->memc_or4
= CONFIG_SYS_CAN_OR
;
834 memctl
->memc_br4
= CONFIG_SYS_CAN_BR
;
836 upmconfig (UPMC
, (uint
*) upmTableFast
,
837 sizeof (upmTableFast
) / sizeof (uint
));
838 memctl
->memc_mcmr
= (MxMR_DSx_3_CYCL
|
844 count
= can_config ();
845 printf ("CAN: %d @ %x\n", count
, CONFIG_SYS_CAN_BASE
);
846 if (hwinf
.can
!= count
) printf("!!! difference to HWIB\n");
848 printf ("CAN: No\n");
853 int board_early_init_r(void)
861 int do_hwib_dump (cmd_tbl_t
* cmdtp
, int flag
, int argc
, char * const argv
[])
868 hwib
, 1, 1, do_hwib_dump
,
873 #ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
874 static int get_flash_timing (void)
876 /* get it from the option -tf in CIB */
877 /* default is 0x00000c84 */
878 int ret
= 0x00000c84;
881 char *p
= (char *) CIB_INFO_START_ADDR
;
883 while ((*p
!= '\0') && (pos
< CIB_INFO_LEN
)) {
884 if (*p
< ' ' || *p
> '~') { /* ASCII strings! */
888 if ((p
[1] == 't') && (p
[2] == 'f')) {
892 if ((*p
>= '0') && (*p
<= '9')) {
897 } else if ((*p
>= 'A') && (*p
<= 'F')) {
903 if (nr
< 8) return 0x00000c84;
915 /* Update the Flash_Size and the Flash Timing */
916 int update_flash_size (int flash_size
)
918 volatile immap_t
* immr
= (immap_t
*)CONFIG_SYS_IMMR
;
919 volatile memctl8260_t
*memctl
= &immr
->im_memctl
;
923 /* I must use reg, otherwise the board hang */
924 reg
= memctl
->memc_or0
;
926 reg
|= MEG_TO_AM(flash_size
>> 20);
927 tim
= get_flash_timing ();
929 reg
|= (tim
& 0xfff);
930 memctl
->memc_or0
= reg
;
936 struct pci_controller hose
;
938 int board_early_init_f (void)
940 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
942 immap
->im_clkrst
.car_sccr
|= M826X_SCCR_PCI_MODE_EN
;
946 extern void pci_mpc8250_init(struct pci_controller
*);
948 void pci_init_board(void)
950 pci_mpc8250_init(&hose
);
954 int board_eth_init(bd_t
*bis
)
956 return pci_eth_init(bis
);