board/tqc/tqm85xx/tqm85xx.c

   1 /*
   2  * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
   3  *
   4  * (C) Copyright 2006
   5  * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de.
   6  *
   7  * (C) Copyright 2005
   8  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   9  *
  10  * Copyright 2004 Freescale Semiconductor.
  11  * (C) Copyright 2002,2003, Motorola Inc.
  12  * Xianghua Xiao, (X.Xiao@motorola.com)
  13  *
  14  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #include <common.h>
  36 #include <pci.h>
  37 #include <asm/processor.h>
  38 #include <asm/immap_85xx.h>
  39 #include <asm/io.h>
  40 #include <ioports.h>
  41 #include <flash.h>
  42 #include <libfdt.h>
  43 #include <fdt_support.h>
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 extern flash_info_t flash_info[];       /* FLASH chips info */
  48
  49 void local_bus_init (void);
  50 ulong flash_get_size (ulong base, int banknum);
  51
  52 #ifdef CONFIG_PS2MULT
  53 void ps2mult_early_init (void);
  54 #endif
  55
  56 #ifdef CONFIG_CPM2
  57 /*
  58  * I/O Port configuration table
  59  *
  60  * if conf is 1, then that port pin will be configured at boot time
  61  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  62  */
  63
  64 const iop_conf_t iop_conf_tab[4][32] = {
  65
  66         /* Port A: conf, ppar, psor, pdir, podr, pdat */
  67         {
  68          {1, 1, 1, 0, 0, 0},    /* PA31: FCC1 MII COL */
  69          {1, 1, 1, 0, 0, 0},    /* PA30: FCC1 MII CRS */
  70          {1, 1, 1, 1, 0, 0},    /* PA29: FCC1 MII TX_ER */
  71          {1, 1, 1, 1, 0, 0},    /* PA28: FCC1 MII TX_EN */
  72          {1, 1, 1, 0, 0, 0},    /* PA27: FCC1 MII RX_DV */
  73          {1, 1, 1, 0, 0, 0},    /* PA26: FCC1 MII RX_ER */
  74          {0, 1, 0, 1, 0, 0},    /* PA25: FCC1 ATMTXD[0] */
  75          {0, 1, 0, 1, 0, 0},    /* PA24: FCC1 ATMTXD[1] */
  76          {0, 1, 0, 1, 0, 0},    /* PA23: FCC1 ATMTXD[2] */
  77          {0, 1, 0, 1, 0, 0},    /* PA22: FCC1 ATMTXD[3] */
  78          {1, 1, 0, 1, 0, 0},    /* PA21: FCC1 MII TxD[3] */
  79          {1, 1, 0, 1, 0, 0},    /* PA20: FCC1 MII TxD[2] */
  80          {1, 1, 0, 1, 0, 0},    /* PA19: FCC1 MII TxD[1] */
  81          {1, 1, 0, 1, 0, 0},    /* PA18: FCC1 MII TxD[0] */
  82          {1, 1, 0, 0, 0, 0},    /* PA17: FCC1 MII RxD[0] */
  83          {1, 1, 0, 0, 0, 0},    /* PA16: FCC1 MII RxD[1] */
  84          {1, 1, 0, 0, 0, 0},    /* PA15: FCC1 MII RxD[2] */
  85          {1, 1, 0, 0, 0, 0},    /* PA14: FCC1 MII RxD[3] */
  86          {0, 1, 0, 0, 0, 0},    /* PA13: FCC1 ATMRXD[3] */
  87          {0, 1, 0, 0, 0, 0},    /* PA12: FCC1 ATMRXD[2] */
  88          {0, 1, 0, 0, 0, 0},    /* PA11: FCC1 ATMRXD[1] */
  89          {0, 1, 0, 0, 0, 0},    /* PA10: FCC1 ATMRXD[0] */
  90          {0, 1, 1, 1, 0, 0},    /* PA9 : FCC1 L1TXD */
  91          {0, 1, 1, 0, 0, 0},    /* PA8 : FCC1 L1RXD */
  92          {0, 0, 0, 1, 0, 0},    /* PA7 : PA7 */
  93          {0, 1, 1, 1, 0, 0},    /* PA6 : TDM A1 L1RSYNC */
  94          {0, 0, 0, 1, 0, 0},    /* PA5 : PA5 */
  95          {0, 0, 0, 1, 0, 0},    /* PA4 : PA4 */
  96          {0, 0, 0, 1, 0, 0},    /* PA3 : PA3 */
  97          {0, 0, 0, 1, 0, 0},    /* PA2 : PA2 */
  98          {0, 0, 0, 0, 0, 0},    /* PA1 : FREERUN */
  99          {0, 0, 0, 1, 0, 0}     /* PA0 : PA0 */
 100          },
 101
 102         /* Port B: conf, ppar, psor, pdir, podr, pdat */
 103         {
 104          {1, 1, 0, 1, 0, 0},    /* PB31: FCC2 MII TX_ER */
 105          {1, 1, 0, 0, 0, 0},    /* PB30: FCC2 MII RX_DV */
 106          {1, 1, 1, 1, 0, 0},    /* PB29: FCC2 MII TX_EN */
 107          {1, 1, 0, 0, 0, 0},    /* PB28: FCC2 MII RX_ER */
 108          {1, 1, 0, 0, 0, 0},    /* PB27: FCC2 MII COL */
 109          {1, 1, 0, 0, 0, 0},    /* PB26: FCC2 MII CRS */
 110          {1, 1, 0, 1, 0, 0},    /* PB25: FCC2 MII TxD[3] */
 111          {1, 1, 0, 1, 0, 0},    /* PB24: FCC2 MII TxD[2] */
 112          {1, 1, 0, 1, 0, 0},    /* PB23: FCC2 MII TxD[1] */
 113          {1, 1, 0, 1, 0, 0},    /* PB22: FCC2 MII TxD[0] */
 114          {1, 1, 0, 0, 0, 0},    /* PB21: FCC2 MII RxD[0] */
 115          {1, 1, 0, 0, 0, 0},    /* PB20: FCC2 MII RxD[1] */
 116          {1, 1, 0, 0, 0, 0},    /* PB19: FCC2 MII RxD[2] */
 117          {1, 1, 0, 0, 0, 0},    /* PB18: FCC2 MII RxD[3] */
 118          {1, 1, 0, 0, 0, 0},    /* PB17: FCC3:RX_DIV */
 119          {1, 1, 0, 0, 0, 0},    /* PB16: FCC3:RX_ERR */
 120          {1, 1, 0, 1, 0, 0},    /* PB15: FCC3:TX_ERR */
 121          {1, 1, 0, 1, 0, 0},    /* PB14: FCC3:TX_EN */
 122          {1, 1, 0, 0, 0, 0},    /* PB13: FCC3:COL */
 123          {1, 1, 0, 0, 0, 0},    /* PB12: FCC3:CRS */
 124          {1, 1, 0, 0, 0, 0},    /* PB11: FCC3:RXD */
 125          {1, 1, 0, 0, 0, 0},    /* PB10: FCC3:RXD */
 126          {1, 1, 0, 0, 0, 0},    /* PB9 : FCC3:RXD */
 127          {1, 1, 0, 0, 0, 0},    /* PB8 : FCC3:RXD */
 128          {1, 1, 0, 1, 0, 0},    /* PB7 : FCC3:TXD */
 129          {1, 1, 0, 1, 0, 0},    /* PB6 : FCC3:TXD */
 130          {1, 1, 0, 1, 0, 0},    /* PB5 : FCC3:TXD */
 131          {1, 1, 0, 1, 0, 0},    /* PB4 : FCC3:TXD */
 132          {0, 0, 0, 0, 0, 0},    /* PB3 : pin doesn't exist */
 133          {0, 0, 0, 0, 0, 0},    /* PB2 : pin doesn't exist */
 134          {0, 0, 0, 0, 0, 0},    /* PB1 : pin doesn't exist */
 135          {0, 0, 0, 0, 0, 0}     /* PB0 : pin doesn't exist */
 136          },
 137
 138         /* Port C: conf, ppar, psor, pdir, podr, pdat */
 139         {
 140          {0, 0, 0, 1, 0, 0},    /* PC31: PC31 */
 141          {0, 0, 0, 1, 0, 0},    /* PC30: PC30 */
 142          {0, 1, 1, 0, 0, 0},    /* PC29: SCC1 EN *CLSN */
 143          {0, 0, 0, 1, 0, 0},    /* PC28: PC28 */
 144          {0, 0, 0, 1, 0, 0},    /* PC27: UART Clock in */
 145          {0, 0, 0, 1, 0, 0},    /* PC26: PC26 */
 146          {0, 0, 0, 1, 0, 0},    /* PC25: PC25 */
 147          {0, 0, 0, 1, 0, 0},    /* PC24: PC24 */
 148          {0, 1, 0, 1, 0, 0},    /* PC23: ATMTFCLK */
 149          {0, 1, 0, 0, 0, 0},    /* PC22: ATMRFCLK */
 150          {1, 1, 0, 0, 0, 0},    /* PC21: SCC1 EN RXCLK */
 151          {1, 1, 0, 0, 0, 0},    /* PC20: SCC1 EN TXCLK */
 152          {1, 1, 0, 0, 0, 0},    /* PC19: FCC2 MII RX_CLK CLK13 */
 153          {1, 1, 0, 0, 0, 0},    /* PC18: FCC Tx Clock (CLK14) */
 154          {1, 1, 0, 0, 0, 0},    /* PC17: PC17 */
 155          {1, 1, 0, 0, 0, 0},    /* PC16: FCC Tx Clock (CLK16) */
 156          {0, 1, 0, 0, 0, 0},    /* PC15: PC15 */
 157          {0, 1, 0, 0, 0, 0},    /* PC14: SCC1 EN *CD */
 158          {0, 1, 0, 0, 0, 0},    /* PC13: PC13 */
 159          {0, 1, 0, 1, 0, 0},    /* PC12: PC12 */
 160          {0, 0, 0, 1, 0, 0},    /* PC11: LXT971 transmit control */
 161          {0, 0, 0, 1, 0, 0},    /* PC10: FETHMDC */
 162          {0, 0, 0, 0, 0, 0},    /* PC9 : FETHMDIO */
 163          {0, 0, 0, 1, 0, 0},    /* PC8 : PC8 */
 164          {0, 0, 0, 1, 0, 0},    /* PC7 : PC7 */
 165          {0, 0, 0, 1, 0, 0},    /* PC6 : PC6 */
 166          {0, 0, 0, 1, 0, 0},    /* PC5 : PC5 */
 167          {0, 0, 0, 1, 0, 0},    /* PC4 : PC4 */
 168          {0, 0, 0, 1, 0, 0},    /* PC3 : PC3 */
 169          {0, 0, 0, 1, 0, 1},    /* PC2 : ENET FDE */
 170          {0, 0, 0, 1, 0, 0},    /* PC1 : ENET DSQE */
 171          {0, 0, 0, 1, 0, 0},    /* PC0 : ENET LBK */
 172          },
 173
 174         /* Port D: conf, ppar, psor, pdir, podr, pdat */
 175         {
 176 #ifdef CONFIG_TQM8560
 177          {1, 1, 0, 0, 0, 0},    /* PD31: SCC1 EN RxD */
 178          {1, 1, 1, 1, 0, 0},    /* PD30: SCC1 EN TxD */
 179          {1, 1, 0, 1, 0, 0},    /* PD29: SCC1 EN TENA */
 180 #else /* !CONFIG_TQM8560 */
 181          {0, 0, 0, 0, 0, 0},    /* PD31: PD31 */
 182          {0, 0, 0, 0, 0, 0},    /* PD30: PD30 */
 183          {0, 0, 0, 0, 0, 0},    /* PD29: PD29 */
 184 #endif /* CONFIG_TQM8560 */
 185          {1, 1, 0, 0, 0, 0},    /* PD28: PD28 */
 186          {1, 1, 0, 1, 0, 0},    /* PD27: PD27 */
 187          {1, 1, 0, 1, 0, 0},    /* PD26: PD26 */
 188          {0, 0, 0, 1, 0, 0},    /* PD25: PD25 */
 189          {0, 0, 0, 1, 0, 0},    /* PD24: PD24 */
 190          {0, 0, 0, 1, 0, 0},    /* PD23: PD23 */
 191          {0, 0, 0, 1, 0, 0},    /* PD22: PD22 */
 192          {0, 0, 0, 1, 0, 0},    /* PD21: PD21 */
 193          {0, 0, 0, 1, 0, 0},    /* PD20: PD20 */
 194          {0, 0, 0, 1, 0, 0},    /* PD19: PD19 */
 195          {0, 0, 0, 1, 0, 0},    /* PD18: PD18 */
 196          {0, 1, 0, 0, 0, 0},    /* PD17: FCC1 ATMRXPRTY */
 197          {0, 1, 0, 1, 0, 0},    /* PD16: FCC1 ATMTXPRTY */
 198          {0, 1, 1, 0, 1, 0},    /* PD15: I2C SDA */
 199          {0, 0, 0, 1, 0, 0},    /* PD14: LED */
 200          {0, 0, 0, 0, 0, 0},    /* PD13: PD13 */
 201          {0, 0, 0, 0, 0, 0},    /* PD12: PD12 */
 202          {0, 0, 0, 0, 0, 0},    /* PD11: PD11 */
 203          {0, 0, 0, 0, 0, 0},    /* PD10: PD10 */
 204          {0, 1, 0, 1, 0, 0},    /* PD9 : SMC1 TXD */
 205          {0, 1, 0, 0, 0, 0},    /* PD8 : SMC1 RXD */
 206          {0, 0, 0, 1, 0, 1},    /* PD7 : PD7 */
 207          {0, 0, 0, 1, 0, 1},    /* PD6 : PD6 */
 208          {0, 0, 0, 1, 0, 1},    /* PD5 : PD5 */
 209          {0, 0, 0, 1, 0, 1},    /* PD4 : PD4 */
 210          {0, 0, 0, 0, 0, 0},    /* PD3 : pin doesn't exist */
 211          {0, 0, 0, 0, 0, 0},    /* PD2 : pin doesn't exist */
 212          {0, 0, 0, 0, 0, 0},    /* PD1 : pin doesn't exist */
 213          {0, 0, 0, 0, 0, 0}     /* PD0 : pin doesn't exist */
 214          }
 215 };
 216 #endif /*  CONFIG_CPM2 */
 217
 218 #define CASL_STRING1    "casl=xx"
 219 #define CASL_STRING2    "casl="
 220
 221 static const int casl_table[] = { 20, 25, 30 };
 222 #define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
 223
 224 int cas_latency (void)
 225 {
 226         char *s = getenv ("serial#");
 227         int casl;
 228         int val;
 229         int i;
 230
 231         casl = CONFIG_DDR_DEFAULT_CL;
 232
 233         if (s != NULL) {
 234                 if (strncmp(s + strlen (s) - strlen (CASL_STRING1),
 235                             CASL_STRING2, strlen (CASL_STRING2)) == 0) {
 236                         val = simple_strtoul (s + strlen (s) - 2, NULL, 10);
 237
 238                         for (i = 0; i < N_CASL; ++i) {
 239                                 if (val == casl_table[i]) {
 240                                         return val;
 241                                 }
 242                         }
 243                 }
 244         }
 245
 246         return casl;
 247 }
 248
 249 int checkboard (void)
 250 {
 251         char *s = getenv ("serial#");
 252
 253         printf ("Board: %s", CONFIG_BOARDNAME);
 254         if (s != NULL) {
 255                 puts (", serial# ");
 256                 puts (s);
 257         }
 258         putc ('\n');
 259
 260 #ifdef CONFIG_PCI
 261         printf ("PCI1:  32 bit, %d MHz (compiled)\n",
 262                 CONFIG_SYS_CLK_FREQ / 1000000);
 263 #else
 264         printf ("PCI1:  disabled\n");
 265 #endif
 266
 267         /*
 268          * Initialize local bus.
 269          */
 270         local_bus_init ();
 271
 272         return 0;
 273 }
 274
 275 int misc_init_r (void)
 276 {
 277         volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
 278
 279         /*
 280          * Adjust flash start and offset to detected values
 281          */
 282         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 283         gd->bd->bi_flashoffset = 0;
 284
 285         /*
 286          * Recalculate CS configuration if second FLASH bank is available
 287          */
 288         if (flash_info[0].size > 0) {
 289                 memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
 290                         (CFG_OR1_PRELIM & 0x00007fff);
 291                 memctl->br1 = gd->bd->bi_flashstart |
 292                         (CFG_BR1_PRELIM & 0x00007fff);
 293                 /*
 294                  * Re-check to get correct base address for bank 1
 295                  */
 296                 flash_get_size (gd->bd->bi_flashstart, 0);
 297         } else {
 298                 memctl->or1 = 0;
 299                 memctl->br1 = 0;
 300         }
 301
 302         /*
 303          *  If bank 1 is equipped, bank 0 is mapped after bank 1
 304          */
 305         memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
 306                 (CFG_OR0_PRELIM & 0x00007fff);
 307         memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
 308                 (CFG_BR0_PRELIM & 0x00007fff);
 309         /*
 310          * Re-check to get correct base address for bank 0
 311          */
 312         flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
 313
 314         /*
 315          * Re-do flash protection upon new addresses
 316          */
 317         flash_protect (FLAG_PROTECT_CLEAR,
 318                        gd->bd->bi_flashstart, 0xffffffff,
 319                        &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 320
 321         /* Monitor protection ON by default */
 322         flash_protect (FLAG_PROTECT_SET,
 323                        CFG_MONITOR_BASE,
 324                        CFG_MONITOR_BASE + monitor_flash_len - 1,
 325                        &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 326
 327         /* Environment protection ON by default */
 328         flash_protect (FLAG_PROTECT_SET,
 329                        CFG_ENV_ADDR,
 330                        CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
 331                        &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 332
 333 #ifdef CFG_ENV_ADDR_REDUND
 334         /* Redundant environment protection ON by default */
 335         flash_protect (FLAG_PROTECT_SET,
 336                        CFG_ENV_ADDR_REDUND,
 337                        CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
 338                        &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 339 #endif
 340
 341         return 0;
 342 }
 343
 344 #ifdef CONFIG_CAN_DRIVER
 345 /*
 346  * Initialize UPMC RAM
 347  */
 348 static void upmc_write (u_char addr, uint val)
 349 {
 350         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 351
 352         out_be32 (&lbc->mdr, val);
 353
 354         clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK,
 355                         MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
 356
 357         /* dummy access to perform write */
 358         out_8 ((void __iomem *)CFG_CAN_BASE, 0);
 359
 360         /* normal operation */
 361         clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
 362 }
 363 #endif /* CONFIG_CAN_DRIVER */
 364
 365 uint get_lbc_clock (void)
 366 {
 367         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 368         sys_info_t sys_info;
 369         ulong clkdiv = lbc->lcrr & 0x0f;
 370
 371         get_sys_info (&sys_info);
 372
 373         if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
 374 #ifdef CONFIG_MPC8548
 375                 /*
 376                  * Yes, the entire PQ38 family use the same
 377                  * bit-representation for twice the clock divider value.
 378                  */
 379                 clkdiv *= 2;
 380 #endif
 381                 return sys_info.freqSystemBus / clkdiv;
 382         }
 383
 384         puts("Invalid clock divider value in CFG_LBC_LCRR\n");
 385
 386         return 0;
 387 }
 388
 389 /*
 390  * Initialize Local Bus
 391  */
 392 void local_bus_init (void)
 393 {
 394         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 395         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 396         uint lbc_mhz = get_lbc_clock ()  / 1000000;
 397
 398 #ifdef CONFIG_MPC8548
 399         uint svr = get_svr ();
 400         uint lcrr;
 401
 402         /*
 403          * MPC revision < 2.0
 404          * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
 405          * Modify engineering use only register at address 0xE_0F20.
 406          * "1. Read register at offset 0xE_0F20
 407          * 2. And value with 0x0000_FFFF
 408          * 3. OR result with 0x0000_0004
 409          * 4. Write result back to offset 0xE_0F20."
 410          *
 411          * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
 412          * Modify engineering use only register at address 0xE_0F20.
 413          * "1. Read register at offset 0xE_0F20
 414          * 2. And value with 0xFFFF_FFDF
 415          * 3. Write result back to offset 0xE_0F20."
 416          *
 417          * Since it is the same register, we do the modification in one step.
 418          */
 419         if (SVR_MAJ (svr) < 2) {
 420                 uint dummy = gur->lbiuiplldcr1;
 421                 dummy &= 0x0000FFDF;
 422                 dummy |= 0x00000004;
 423                 gur->lbiuiplldcr1 = dummy;
 424         }
 425
 426         lcrr = CFG_LBC_LCRR;
 427
 428         /*
 429          * Local Bus Clock > 83.3 MHz. According to timing
 430          * specifications set LCRR[EADC] to 2 delay cycles.
 431          */
 432         if (lbc_mhz > 83) {
 433                 lcrr &= ~LCRR_EADC;
 434                 lcrr |= LCRR_EADC_2;
 435         }
 436
 437         /*
 438          * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
 439          * disable PLL bypass for Local Bus Clock > 83 MHz.
 440          */
 441         if (lbc_mhz >= 66)
 442                 lcrr &= (~LCRR_DBYP);   /* DLL Enabled */
 443
 444         else
 445                 lcrr |= LCRR_DBYP;      /* DLL Bypass */
 446
 447         lbc->lcrr = lcrr;
 448         asm ("sync;isync;msync");
 449
 450         /*
 451          * According to MPC8548ERMAD Rev.1.3 read back LCRR
 452          * and terminate with isync
 453          */
 454         lcrr = lbc->lcrr;
 455         asm ("isync;");
 456
 457         /* let DLL stabilize */
 458         udelay (500);
 459
 460 #else /* !CONFIG_MPC8548 */
 461
 462         /*
 463          * Errata LBC11.
 464          * Fix Local Bus clock glitch when DLL is enabled.
 465          *
 466          * If localbus freq is < 66Mhz, DLL bypass mode must be used.
 467          * If localbus freq is > 133Mhz, DLL can be safely enabled.
 468          * Between 66 and 133, the DLL is enabled with an override workaround.
 469          */
 470
 471         if (lbc_mhz < 66) {
 472                 lbc->lcrr = CFG_LBC_LCRR | LCRR_DBYP;   /* DLL Bypass */
 473                 lbc->ltedr = 0xa4c80000;        /* DK: !!! */
 474
 475         } else if (lbc_mhz >= 133) {
 476                 lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP);        /* DLL Enabled */
 477
 478         } else {
 479                 /*
 480                  * On REV1 boards, need to change CLKDIV before enable DLL.
 481                  * Default CLKDIV is 8, change it to 4 temporarily.
 482                  */
 483                 uint pvr = get_pvr ();
 484                 uint temp_lbcdll = 0;
 485
 486                 if (pvr == PVR_85xx_REV1) {
 487                         /* FIXME: Justify the high bit here. */
 488                         lbc->lcrr = 0x10000004;
 489                 }
 490
 491                 lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP);        /* DLL Enabled */
 492                 udelay (200);
 493
 494                 /*
 495                  * Sample LBC DLL ctrl reg, upshift it to set the
 496                  * override bits.
 497                  */
 498                 temp_lbcdll = gur->lbcdllcr;
 499                 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 500                 asm ("sync;isync;msync");
 501         }
 502 #endif /* !CONFIG_MPC8548 */
 503
 504 #ifdef  CONFIG_CAN_DRIVER
 505         /*
 506          * According to timing specifications EAD must be
 507          * set if Local Bus Clock is > 83 MHz.
 508          */
 509         if (lbc_mhz > 83)
 510                 out_be32 (&lbc->or2, CFG_OR2_CAN | OR_UPM_EAD);
 511         else
 512                 out_be32 (&lbc->or2, CFG_OR2_CAN);
 513         out_be32 (&lbc->br2, CFG_BR2_CAN);
 514
 515         /* LGPL4 is UPWAIT */
 516         out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
 517
 518         /* Initialize UPMC for CAN: single read */
 519         upmc_write (0x00, 0xFFFFED00);
 520         upmc_write (0x01, 0xCCFFCC00);
 521         upmc_write (0x02, 0x00FFCF00);
 522         upmc_write (0x03, 0x00FFCF00);
 523         upmc_write (0x04, 0x00FFDC00);
 524         upmc_write (0x05, 0x00FFCF00);
 525         upmc_write (0x06, 0x00FFED00);
 526         upmc_write (0x07, 0x3FFFCC07);
 527
 528         /* Initialize UPMC for CAN: single write */
 529         upmc_write (0x18, 0xFFFFED00);
 530         upmc_write (0x19, 0xCCFFEC00);
 531         upmc_write (0x1A, 0x00FFED80);
 532         upmc_write (0x1B, 0x00FFED80);
 533         upmc_write (0x1C, 0x00FFFC00);
 534         upmc_write (0x1D, 0x0FFFEC00);
 535         upmc_write (0x1E, 0x0FFFEF00);
 536         upmc_write (0x1F, 0x3FFFEC05);
 537 #endif /* CONFIG_CAN_DRIVER */
 538 }
 539
 540 #if defined(CONFIG_PCI)
 541 /*
 542  * Initialize PCI Devices, report devices found.
 543  */
 544
 545 #ifndef CONFIG_PCI_PNP
 546 static struct pci_config_table pci_mpc85xxads_config_table[] = {
 547         {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 548          PCI_IDSEL_NUMBER, PCI_ANY_ID,
 549          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 550                                      PCI_ENET0_MEMADDR,
 551                                      PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
 552         {}
 553 };
 554 #endif
 555
 556 static struct pci_controller hose = {
 557 #ifndef CONFIG_PCI_PNP
 558       config_table:pci_mpc85xxads_config_table,
 559 #endif
 560 };
 561
 562 #endif /* CONFIG_PCI */
 563
 564 void pci_init_board (void)
 565 {
 566 #ifdef CONFIG_PCI
 567         pci_mpc85xx_init (&hose);
 568 #endif /* CONFIG_PCI */
 569 }
 570
 571 #if defined(CONFIG_OF_BOARD_SETUP)
 572 void ft_board_setup (void *blob, bd_t *bd)
 573 {
 574         int node, tmp[2];
 575         const char *path;
 576
 577         ft_cpu_setup (blob, bd);
 578
 579         node = fdt_path_offset (blob, "/aliases");
 580         tmp[0] = 0;
 581         if (node >= 0) {
 582 #ifdef CONFIG_PCI
 583                 path = fdt_getprop (blob, node, "pci0", NULL);
 584                 if (path) {
 585                         tmp[1] = hose.last_busno - hose.first_busno;
 586                         do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
 587                 }
 588 #endif
 589         }
 590 }
 591 #endif
 592
 593 #ifdef CONFIG_BOARD_EARLY_INIT_R
 594 int board_early_init_r (void)
 595 {
 596 #ifdef CONFIG_PS2MULT
 597         ps2mult_early_init ();
 598 #endif /* CONFIG_PS2MULT */
 599         return (0);
 600 }
 601 #endif /* CONFIG_BOARD_EARLY_INIT_R */