board/tqc/tqm8xx/tqm8xx.c

   1 /*
   2  * (C) Copyright 2000-2008
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <mpc8xx.h>
  26 #ifdef CONFIG_PS2MULT
  27 #include <ps2mult.h>
  28 #endif
  29
  30 extern flash_info_t flash_info[];       /* FLASH chips info */
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 static long int dram_size (long int, long int *, long int);
  35
  36 #define _NOT_USED_      0xFFFFFFFF
  37
  38 /* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
  39 const uint sdram_table[] =
  40 {
  41         /*
  42          * Single Read. (Offset 0 in UPMA RAM)
  43          */
  44         0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
  45         0x1FF5FC47, /* last */
  46         /*
  47          * SDRAM Initialization (offset 5 in UPMA RAM)
  48          *
  49          * This is no UPM entry point. The following definition uses
  50          * the remaining space to establish an initialization
  51          * sequence, which is executed by a RUN command.
  52          *
  53          */
  54                     0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
  55         /*
  56          * Burst Read. (Offset 8 in UPMA RAM)
  57          */
  58         0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
  59         0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
  60         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  61         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  62         /*
  63          * Single Write. (Offset 18 in UPMA RAM)
  64          */
  65         0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
  66         0x1FF5FC47, /* last */
  67                     _NOT_USED_, _NOT_USED_, _NOT_USED_,
  68         /*
  69          * Burst Write. (Offset 20 in UPMA RAM)
  70          */
  71         0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
  72         0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
  73         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  74         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  75         /*
  76          * Refresh  (Offset 30 in UPMA RAM)
  77          */
  78         0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  79         0xFFFFFC84, 0xFFFFFC07, /* last */
  80                                 _NOT_USED_, _NOT_USED_,
  81         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  82         /*
  83          * Exception. (Offset 3c in UPMA RAM)
  84          */
  85         0xFFFFFC07, /* last */
  86                     _NOT_USED_, _NOT_USED_, _NOT_USED_,
  87 };
  88
  89 /* ------------------------------------------------------------------------- */
  90
  91
  92 /*
  93  * Check Board Identity:
  94  *
  95  * Test TQ ID string (TQM8xx...)
  96  * If present, check for "L" type (no second DRAM bank),
  97  * otherwise "L" type is assumed as default.
  98  *
  99  * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
 100  */
 101
 102 int checkboard (void)
 103 {
 104         char *s = getenv ("serial#");
 105
 106         puts ("Board: ");
 107
 108         if (!s || strncmp (s, "TQM8", 4)) {
 109                 puts ("### No HW ID - assuming TQM8xxL\n");
 110                 return (0);
 111         }
 112
 113         if ((*(s + 6) == 'L')) {        /* a TQM8xxL type */
 114                 gd->board_type = 'L';
 115         }
 116
 117         if ((*(s + 6) == 'M')) {        /* a TQM8xxM type */
 118                 gd->board_type = 'M';
 119         }
 120
 121         if ((*(s + 6) == 'D')) {        /* a TQM885D type */
 122                 gd->board_type = 'D';
 123         }
 124
 125         for (; *s; ++s) {
 126                 if (*s == ' ')
 127                         break;
 128                 putc (*s);
 129         }
 130 #ifdef CONFIG_VIRTLAB2
 131         puts (" (Virtlab2)");
 132 #endif
 133         putc ('\n');
 134
 135         return (0);
 136 }
 137
 138 /* ------------------------------------------------------------------------- */
 139
 140 phys_size_t initdram (int board_type)
 141 {
 142         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 143         volatile memctl8xx_t *memctl = &immap->im_memctl;
 144         long int size8, size9, size10;
 145         long int size_b0 = 0;
 146         long int size_b1 = 0;
 147
 148         upmconfig (UPMA, (uint *) sdram_table,
 149                            sizeof (sdram_table) / sizeof (uint));
 150
 151         /*
 152          * Preliminary prescaler for refresh (depends on number of
 153          * banks): This value is selected for four cycles every 62.4 us
 154          * with two SDRAM banks or four cycles every 31.2 us with one
 155          * bank. It will be adjusted after memory sizing.
 156          */
 157         memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 158
 159         /*
 160          * The following value is used as an address (i.e. opcode) for
 161          * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
 162          * the port size is 32bit the SDRAM does NOT "see" the lower two
 163          * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
 164          * MICRON SDRAMs:
 165          * ->    0 00 010 0 010
 166          *       |  |   | |   +- Burst Length = 4
 167          *       |  |   | +----- Burst Type   = Sequential
 168          *       |  |   +------- CAS Latency  = 2
 169          *       |  +----------- Operating Mode = Standard
 170          *       +-------------- Write Burst Mode = Programmed Burst Length
 171          */
 172         memctl->memc_mar = 0x00000088;
 173
 174         /*
 175          * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
 176          * preliminary addresses - these have to be modified after the
 177          * SDRAM size has been determined.
 178          */
 179         memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
 180         memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 181
 182 #ifndef CONFIG_CAN_DRIVER
 183         if ((board_type != 'L') &&
 184             (board_type != 'M') &&
 185             (board_type != 'D') ) {     /* only one SDRAM bank on L, M and D modules */
 186                 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
 187                 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 188         }
 189 #endif                                                  /* CONFIG_CAN_DRIVER */
 190
 191         memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));      /* no refresh yet */
 192
 193         udelay (200);
 194
 195         /* perform SDRAM initializsation sequence */
 196
 197         memctl->memc_mcr = 0x80004105;  /* SDRAM bank 0 */
 198         udelay (1);
 199         memctl->memc_mcr = 0x80004230;  /* SDRAM bank 0 - execute twice */
 200         udelay (1);
 201
 202 #ifndef CONFIG_CAN_DRIVER
 203         if ((board_type != 'L') &&
 204             (board_type != 'M') &&
 205             (board_type != 'D') ) {     /* only one SDRAM bank on L, M and D modules */
 206                 memctl->memc_mcr = 0x80006105;  /* SDRAM bank 1 */
 207                 udelay (1);
 208                 memctl->memc_mcr = 0x80006230;  /* SDRAM bank 1 - execute twice */
 209                 udelay (1);
 210         }
 211 #endif                                                  /* CONFIG_CAN_DRIVER */
 212
 213         memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 214
 215         udelay (1000);
 216
 217         /*
 218          * Check Bank 0 Memory Size for re-configuration
 219          *
 220          * try 8 column mode
 221          */
 222         size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
 223         debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
 224
 225         udelay (1000);
 226
 227         /*
 228          * try 9 column mode
 229          */
 230         size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
 231         debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
 232
 233         udelay(1000);
 234
 235 #if defined(CONFIG_SYS_MAMR_10COL)
 236         /*
 237          * try 10 column mode
 238          */
 239         size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
 240         debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
 241 #else
 242         size10 = 0;
 243 #endif /* CONFIG_SYS_MAMR_10COL */
 244
 245         if ((size8 < size10) && (size9 < size10)) {
 246                 size_b0 = size10;
 247         } else if ((size8 < size9) && (size10 < size9)) {
 248                 size_b0 = size9;
 249                 memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
 250                 udelay (500);
 251         } else {
 252                 size_b0 = size8;
 253                 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 254                 udelay (500);
 255         }
 256         debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
 257
 258 #ifndef CONFIG_CAN_DRIVER
 259         if ((board_type != 'L') &&
 260             (board_type != 'M') &&
 261             (board_type != 'D') ) {     /* only one SDRAM bank on L, M and D modules */
 262                 /*
 263                  * Check Bank 1 Memory Size
 264                  * use current column settings
 265                  * [9 column SDRAM may also be used in 8 column mode,
 266                  *  but then only half the real size will be used.]
 267                  */
 268                 size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
 269                                      SDRAM_MAX_SIZE);
 270                 debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
 271         } else {
 272                 size_b1 = 0;
 273         }
 274 #endif  /* CONFIG_CAN_DRIVER */
 275
 276         udelay (1000);
 277
 278         /*
 279          * Adjust refresh rate depending on SDRAM type, both banks
 280          * For types > 128 MBit leave it at the current (fast) rate
 281          */
 282         if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
 283                 /* reduce to 15.6 us (62.4 us / quad) */
 284                 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 285                 udelay (1000);
 286         }
 287
 288         /*
 289          * Final mapping: map bigger bank first
 290          */
 291         if (size_b1 > size_b0) {        /* SDRAM Bank 1 is bigger - map first   */
 292
 293                 memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 294                 memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 295
 296                 if (size_b0 > 0) {
 297                         /*
 298                          * Position Bank 0 immediately above Bank 1
 299                          */
 300                         memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 301                         memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 302                                            + size_b1;
 303                 } else {
 304                         unsigned long reg;
 305
 306                         /*
 307                          * No bank 0
 308                          *
 309                          * invalidate bank
 310                          */
 311                         memctl->memc_br2 = 0;
 312
 313                         /* adjust refresh rate depending on SDRAM type, one bank */
 314                         reg = memctl->memc_mptpr;
 315                         reg >>= 1;                      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 316                         memctl->memc_mptpr = reg;
 317                 }
 318
 319         } else {                                        /* SDRAM Bank 0 is bigger - map first   */
 320
 321                 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 322                 memctl->memc_br2 =
 323                                 (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 324
 325                 if (size_b1 > 0) {
 326                         /*
 327                          * Position Bank 1 immediately above Bank 0
 328                          */
 329                         memctl->memc_or3 =
 330                                         ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 331                         memctl->memc_br3 =
 332                                         ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 333                                         + size_b0;
 334                 } else {
 335                         unsigned long reg;
 336
 337 #ifndef CONFIG_CAN_DRIVER
 338                         /*
 339                          * No bank 1
 340                          *
 341                          * invalidate bank
 342                          */
 343                         memctl->memc_br3 = 0;
 344 #endif                                                  /* CONFIG_CAN_DRIVER */
 345
 346                         /* adjust refresh rate depending on SDRAM type, one bank */
 347                         reg = memctl->memc_mptpr;
 348                         reg >>= 1;                      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 349                         memctl->memc_mptpr = reg;
 350                 }
 351         }
 352
 353         udelay (10000);
 354
 355 #ifdef  CONFIG_CAN_DRIVER
 356         /* UPM initialization for CAN @ CLKOUT <= 66 MHz */
 357
 358         /* Initialize OR3 / BR3 */
 359         memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
 360         memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
 361
 362         /* Initialize MBMR */
 363         memctl->memc_mbmr = MBMR_GPL_B4DIS;     /* GPL_B4 ouput line Disable */
 364
 365         /* Initialize UPMB for CAN: single read */
 366         memctl->memc_mdr = 0xFFFFCC04;
 367         memctl->memc_mcr = 0x0100 | UPMB;
 368
 369         memctl->memc_mdr = 0x0FFFD004;
 370         memctl->memc_mcr = 0x0101 | UPMB;
 371
 372         memctl->memc_mdr = 0x0FFFC000;
 373         memctl->memc_mcr = 0x0102 | UPMB;
 374
 375         memctl->memc_mdr = 0x3FFFC004;
 376         memctl->memc_mcr = 0x0103 | UPMB;
 377
 378         memctl->memc_mdr = 0xFFFFDC07;
 379         memctl->memc_mcr = 0x0104 | UPMB;
 380
 381         /* Initialize UPMB for CAN: single write */
 382         memctl->memc_mdr = 0xFFFCCC04;
 383         memctl->memc_mcr = 0x0118 | UPMB;
 384
 385         memctl->memc_mdr = 0xCFFCDC04;
 386         memctl->memc_mcr = 0x0119 | UPMB;
 387
 388         memctl->memc_mdr = 0x3FFCC000;
 389         memctl->memc_mcr = 0x011A | UPMB;
 390
 391         memctl->memc_mdr = 0xFFFCC004;
 392         memctl->memc_mcr = 0x011B | UPMB;
 393
 394         memctl->memc_mdr = 0xFFFDC405;
 395         memctl->memc_mcr = 0x011C | UPMB;
 396 #endif                                                  /* CONFIG_CAN_DRIVER */
 397
 398 #ifdef  CONFIG_ISP1362_USB
 399         /* Initialize OR5 / BR5 */
 400         memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362;
 401         memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362;
 402 #endif                                                  /* CONFIG_ISP1362_USB */
 403         return (size_b0 + size_b1);
 404 }
 405
 406 /* ------------------------------------------------------------------------- */
 407
 408 /*
 409  * Check memory range for valid RAM. A simple memory test determines
 410  * the actually available RAM size between addresses `base' and
 411  * `base + maxsize'. Some (not all) hardware errors are detected:
 412  * - short between address lines
 413  * - short between data lines
 414  */
 415
 416 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 417 {
 418         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 419         volatile memctl8xx_t *memctl = &immap->im_memctl;
 420
 421         memctl->memc_mamr = mamr_value;
 422
 423         return (get_ram_size(base, maxsize));
 424 }
 425
 426 /* ------------------------------------------------------------------------- */
 427
 428 #ifdef CONFIG_PS2MULT
 429
 430 #ifdef CONFIG_HMI10
 431 #define BASE_BAUD ( 1843200 / 16 )
 432 struct serial_state rs_table[] = {
 433         { BASE_BAUD, 4,  (void*)0xec140000 },
 434         { BASE_BAUD, 2,  (void*)0xec150000 },
 435         { BASE_BAUD, 6,  (void*)0xec160000 },
 436         { BASE_BAUD, 10, (void*)0xec170000 },
 437 };
 438
 439 #ifdef CONFIG_BOARD_EARLY_INIT_R
 440 int board_early_init_r (void)
 441 {
 442         ps2mult_early_init();
 443         return (0);
 444 }
 445 #endif
 446 #endif /* CONFIG_HMI10 */
 447
 448 #endif /* CONFIG_PS2MULT */
 449
 450
 451 #ifdef CONFIG_MISC_INIT_R
 452 extern void load_sernum_ethaddr(void);
 453 int misc_init_r (void)
 454 {
 455         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 456         volatile memctl8xx_t *memctl = &immap->im_memctl;
 457
 458         load_sernum_ethaddr();
 459
 460 #ifdef  CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
 461         int scy, trlx, flash_or_timing, clk_diff;
 462
 463         scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
 464         if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
 465                 trlx = OR_TRLX;
 466                 scy *= 2;
 467         } else {
 468                 trlx = 0;
 469         }
 470
 471         /*
 472          * We assume that each 10MHz of bus clock require 1-clk SCY
 473          * adjustment.
 474          */
 475         clk_diff = (gd->bus_clk / 1000000) - 50;
 476
 477         /*
 478          * We need proper rounding here. This is what the "+5" and "-5"
 479          * are here for.
 480          */
 481         if (clk_diff >= 0)
 482                 scy += (clk_diff + 5) / 10;
 483         else
 484                 scy += (clk_diff - 5) / 10;
 485
 486         /*
 487          * For bus frequencies above 50MHz, we want to use relaxed timing
 488          * (OR_TRLX).
 489          */
 490         if (gd->bus_clk >= 50000000)
 491                 trlx = OR_TRLX;
 492         else
 493                 trlx = 0;
 494
 495         if (trlx)
 496                 scy /= 2;
 497
 498         if (scy > 0xf)
 499                 scy = 0xf;
 500         if (scy < 1)
 501                 scy = 1;
 502
 503         flash_or_timing = (scy << 4) | trlx |
 504                 (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
 505
 506         memctl->memc_or0 =
 507                 flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
 508 #else
 509         memctl->memc_or0 =
 510                 CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
 511 #endif
 512         memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 513
 514         debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
 515                memctl->memc_br0, memctl->memc_or0);
 516
 517         if (flash_info[1].size) {
 518 #ifdef  CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
 519                 memctl->memc_or1 = flash_or_timing |
 520                         (-flash_info[1].size & 0xFFFF8000);
 521 #else
 522                 memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
 523                         (-flash_info[1].size & 0xFFFF8000);
 524 #endif
 525                 memctl->memc_br1 =
 526                         ((CONFIG_SYS_FLASH_BASE +
 527                           flash_info[0].
 528                           size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 529
 530                 debug ("## BR1: 0x%08x    OR1: 0x%08x\n",
 531                        memctl->memc_br1, memctl->memc_or1);
 532         } else {
 533                 memctl->memc_br1 = 0;   /* invalidate bank */
 534
 535                 debug ("## DISABLE BR1: 0x%08x    OR1: 0x%08x\n",
 536                        memctl->memc_br1, memctl->memc_or1);
 537         }
 538
 539 # ifdef CONFIG_IDE_LED
 540         /* Configure PA15 as output port */
 541         immap->im_ioport.iop_padir |= 0x0001;
 542         immap->im_ioport.iop_paodr |= 0x0001;
 543         immap->im_ioport.iop_papar &= ~0x0001;
 544         immap->im_ioport.iop_padat &= ~0x0001;  /* turn it off */
 545 # endif
 546
 547 #ifdef CONFIG_NSCU
 548         /* wake up ethernet module */
 549         immap->im_ioport.iop_pcpar &= ~0x0004;  /* GPIO pin      */
 550         immap->im_ioport.iop_pcdir |= 0x0004;   /* output        */
 551         immap->im_ioport.iop_pcso &= ~0x0004;   /* for clarity   */
 552         immap->im_ioport.iop_pcdat |= 0x0004;   /* enable        */
 553 #endif /* CONFIG_NSCU */
 554
 555         return (0);
 556 }
 557 #endif  /* CONFIG_MISC_INIT_R */
 558
 559
 560 # ifdef CONFIG_IDE_LED
 561 void ide_led (uchar led, uchar status)
 562 {
 563         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 564
 565         /* We have one led for both pcmcia slots */
 566         if (status) {                           /* led on */
 567                 immap->im_ioport.iop_padat |= 0x0001;
 568         } else {
 569                 immap->im_ioport.iop_padat &= ~0x0001;
 570         }
 571 }
 572 # endif
 573
 574 #ifdef CONFIG_LCD_INFO
 575 #include <lcd.h>
 576 #include <version.h>
 577 #include <timestamp.h>
 578
 579 void lcd_show_board_info(void)
 580 {
 581         char temp[32];
 582
 583         lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
 584         lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
 585         lcd_printf ("    Wolfgang DENK, wd@denx.de\n");
 586 #ifdef CONFIG_LCD_INFO_BELOW_LOGO
 587         lcd_printf ("MPC823 CPU at %s MHz\n",
 588                 strmhz(temp, gd->cpu_clk));
 589         lcd_printf ("  %ld MB RAM, %ld MB Flash\n",
 590                 gd->ram_size >> 20,
 591                 gd->bd->bi_flashsize >> 20 );
 592 #else
 593         /* leave one blank line */
 594         lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n",
 595                 strmhz(temp, gd->cpu_clk),
 596                 gd->ram_size >> 20,
 597                 gd->bd->bi_flashsize >> 20 );
 598 #endif /* CONFIG_LCD_INFO_BELOW_LOGO */
 599 }
 600 #endif /* CONFIG_LCD_INFO */
 601
 602 /* ---------------------------------------------------------------------------- */
 603 /* TK885D specific initializaion                                                */
 604 /* ---------------------------------------------------------------------------- */
 605 #ifdef CONFIG_TK885D
 606 #include <miiphy.h>
 607 int last_stage_init(void)
 608 {
 609         const unsigned char phy[] = {CONFIG_FEC1_PHY, CONFIG_FEC2_PHY};
 610         unsigned short reg;
 611         int ret, i = 100;
 612         char *s;
 613
 614         mii_init();
 615         /* Without this delay 0xff is read from the UART buffer later in
 616          * abortboot() and autoboot is aborted */
 617         udelay(10000);
 618         while (tstc() && i--)
 619                 (void)getc();
 620
 621         /* Check if auto-negotiation is prohibited */
 622         s = getenv("phy_auto_nego");
 623
 624         if (!s || !strcmp(s, "on"))
 625                 /* Nothing to do - autonegotiation by default */
 626                 return 0;
 627
 628         for (i = 0; i < 2; i++) {
 629                 ret = miiphy_read("FEC ETHERNET", phy[i], PHY_BMCR, &reg);
 630                 if (ret) {
 631                         printf("Cannot read BMCR on PHY %d\n", phy[i]);
 632                         return 0;
 633                 }
 634                 /* Auto-negotiation off, hard set full duplex, 100Mbps */
 635                 ret = miiphy_write("FEC ETHERNET", phy[i],
 636                                    PHY_BMCR, (reg | PHY_BMCR_100MB |
 637                                               PHY_BMCR_DPLX) & ~PHY_BMCR_AUTON);
 638                 if (ret) {
 639                         printf("Cannot write BMCR on PHY %d\n", phy[i]);
 640                         return 0;
 641                 }
 642         }
 643
 644         return 0;
 645 }
 646 #endif