board/tqc/tqma6/tqma6_mba6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
   7  * Author: Markus Niebel <markus.niebel@tq-group.com>
   8  */
   9
  10 #include <init.h>
  11 #include <net.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/iomux.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <linux/errno.h>
  19 #include <asm/gpio.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21
  22 #include <common.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <linux/libfdt.h>
  25 #include <malloc.h>
  26 #include <i2c.h>
  27 #include <micrel.h>
  28 #include <miiphy.h>
  29 #include <mmc.h>
  30 #include <netdev.h>
  31
  32 #include "tqma6_bb.h"
  33
  34 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  35         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  36
  37 #define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
  38         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
  41         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  42
  43 #define GPIO_OUT_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  44         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  45
  46 #define GPIO_IN_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  47         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  48
  49 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  50         PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  51
  52 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  53         PAD_CTL_DSE_80ohm | PAD_CTL_HYS |                       \
  54         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  55
  56 #if defined(CONFIG_TQMA6Q)
  57
  58 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII    0x02e0790
  59 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM        0x02e07ac
  60
  61 #elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
  62
  63 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII    0x02e0768
  64 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM        0x02e0788
  65
  66 #else
  67
  68 #error "need to select module"
  69
  70 #endif
  71
  72 /* disable on die termination for RGMII */
  73 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE        0x00000000
  74 /* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
  75 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V       0x00080000
  76 /* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
  77 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V       0x000C0000
  78
  79 static void mba6_setup_iomuxc_enet(void)
  80 {
  81         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  82
  83         /* clear gpr1[ENET_CLK_SEL] for externel clock */
  84         clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
  85
  86         __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
  87                      (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
  88         __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
  89                      (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
  90 }
  91
  92 static iomux_v3_cfg_t const mba6_uart2_pads[] = {
  93         NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
  94         NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
  95 };
  96
  97 static void mba6_setup_iomuxc_uart(void)
  98 {
  99         imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
 100                                          ARRAY_SIZE(mba6_uart2_pads));
 101 }
 102
 103 int board_mmc_get_env_dev(int devno)
 104 {
 105         /*
 106          * This assumes that the baseboard registered
 107          * the boot device first ...
 108          * Note: SDHC3 == idx2
 109          */
 110         return (2 == devno) ? 0 : 1;
 111 }
 112
 113 int board_phy_config(struct phy_device *phydev)
 114 {
 115 /*
 116  * optimized pad skew values depends on CPU variant on the TQMa6x module:
 117  * CONFIG_TQMA6Q: i.MX6Q/D
 118  * CONFIG_TQMA6S: i.MX6S
 119  * CONFIG_TQMA6DL: i.MX6DL
 120  */
 121 #if defined(CONFIG_TQMA6Q)
 122 #define MBA6X_KSZ9031_CTRL_SKEW 0x0032
 123 #define MBA6X_KSZ9031_CLK_SKEW  0x03ff
 124 #define MBA6X_KSZ9031_RX_SKEW   0x3333
 125 #define MBA6X_KSZ9031_TX_SKEW   0x2036
 126 #elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
 127 #define MBA6X_KSZ9031_CTRL_SKEW 0x0030
 128 #define MBA6X_KSZ9031_CLK_SKEW  0x03ff
 129 #define MBA6X_KSZ9031_RX_SKEW   0x3333
 130 #define MBA6X_KSZ9031_TX_SKEW   0x2052
 131 #else
 132 #error
 133 #endif
 134         /* min rx/tx ctrl delay */
 135         ksz9031_phy_extended_write(phydev, 2,
 136                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 137                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
 138                                    MBA6X_KSZ9031_CTRL_SKEW);
 139         /* min rx delay */
 140         ksz9031_phy_extended_write(phydev, 2,
 141                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 142                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
 143                                    MBA6X_KSZ9031_RX_SKEW);
 144         /* max tx delay */
 145         ksz9031_phy_extended_write(phydev, 2,
 146                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 147                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
 148                                    MBA6X_KSZ9031_TX_SKEW);
 149         /* rx/tx clk skew */
 150         ksz9031_phy_extended_write(phydev, 2,
 151                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 152                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
 153                                    MBA6X_KSZ9031_CLK_SKEW);
 154
 155         phydev->drv->config(phydev);
 156
 157         return 0;
 158 }
 159
 160 int tqma6_bb_board_early_init_f(void)
 161 {
 162         mba6_setup_iomuxc_uart();
 163
 164         return 0;
 165 }
 166
 167 int tqma6_bb_board_init(void)
 168 {
 169         mba6_setup_iomuxc_enet();
 170
 171         return 0;
 172 }
 173
 174 int tqma6_bb_board_late_init(void)
 175 {
 176         return 0;
 177 }
 178
 179 const char *tqma6_bb_get_boardname(void)
 180 {
 181         return "MBa6x";
 182 }
 183
 184 /*
 185  * Device Tree Support
 186  */
 187 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
 188 void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
 189 {
 190  /* TBD */
 191 }
 192 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */