2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
6 * Author: Markus Niebel <markus.niebel@tq-group.com>
8 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/clock.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/iomux.h>
18 #include <asm/arch/sys_proto.h>
19 #include <linux/errno.h>
21 #include <asm/mach-imx/boot_mode.h>
22 #include <asm/mach-imx/mxc_i2c.h>
25 #include <fsl_esdhc.h>
26 #include <linux/libfdt.h>
37 #define UART4_PAD_CTRL ( \
39 PAD_CTL_PUS_100K_UP | \
47 static iomux_v3_cfg_t
const uart4_pads
[] = {
48 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT17__UART4_CTS_B
, UART4_PAD_CTRL
),
49 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT16__UART4_RTS_B
, UART4_PAD_CTRL
),
50 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT13__UART4_RX_DATA
, UART4_PAD_CTRL
),
51 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT12__UART4_TX_DATA
, UART4_PAD_CTRL
),
54 static void setup_iomuxc_uart4(void)
56 imx_iomux_v3_setup_multiple_pads(uart4_pads
, ARRAY_SIZE(uart4_pads
));
60 #define USDHC2_PAD_CTRL ( \
62 PAD_CTL_PUS_47K_UP | \
68 #define USDHC2_CLK_PAD_CTRL ( \
70 PAD_CTL_PUS_47K_UP | \
76 static iomux_v3_cfg_t
const usdhc2_pads
[] = {
77 NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK
, USDHC2_CLK_PAD_CTRL
),
78 NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD
, USDHC2_PAD_CTRL
),
79 NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0
, USDHC2_PAD_CTRL
),
80 NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1
, USDHC2_PAD_CTRL
),
81 NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2
, USDHC2_PAD_CTRL
),
82 NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3
, USDHC2_PAD_CTRL
),
84 NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04
, USDHC2_PAD_CTRL
), /* CD */
85 NEW_PAD_CTRL(MX6_PAD_GPIO_2__SD2_WP
, USDHC2_PAD_CTRL
), /* WP */
88 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
89 #define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
91 static struct fsl_esdhc_cfg usdhc2_cfg
= {
92 .esdhc_base
= USDHC2_BASE_ADDR
,
96 int tqma6_bb_board_mmc_getcd(struct mmc
*mmc
)
98 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
101 if (cfg
->esdhc_base
== USDHC2_BASE_ADDR
)
102 ret
= !gpio_get_value(USDHC2_CD_GPIO
);
107 int tqma6_bb_board_mmc_getwp(struct mmc
*mmc
)
109 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
112 if (cfg
->esdhc_base
== USDHC2_BASE_ADDR
)
113 ret
= gpio_get_value(USDHC2_WP_GPIO
);
118 int tqma6_bb_board_mmc_init(bd_t
*bis
)
122 imx_iomux_v3_setup_multiple_pads(usdhc2_pads
, ARRAY_SIZE(usdhc2_pads
));
124 ret
= gpio_request(USDHC2_CD_GPIO
, "mmc-cd");
126 gpio_direction_input(USDHC2_CD_GPIO
);
127 ret
= gpio_request(USDHC2_WP_GPIO
, "mmc-wp");
129 gpio_direction_input(USDHC2_WP_GPIO
);
131 usdhc2_cfg
.sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
132 if(fsl_esdhc_initialize(bis
, &usdhc2_cfg
))
133 puts("WARNING: failed to initialize SD\n");
139 #define ENET_PAD_CTRL ( \
141 PAD_CTL_PUS_100K_UP | \
144 PAD_CTL_SPEED_MED | \
145 PAD_CTL_DSE_40ohm | \
149 static iomux_v3_cfg_t
const enet_pads
[] = {
150 NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC
, ENET_PAD_CTRL
),
151 NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO
, ENET_PAD_CTRL
),
152 NEW_PAD_CTRL(MX6_PAD_GPIO_16__ENET_REF_CLK
, ENET_PAD_CTRL
),
153 NEW_PAD_CTRL(MX6_PAD_ENET_RXD0__ENET_RX_DATA0
, ENET_PAD_CTRL
),
154 NEW_PAD_CTRL(MX6_PAD_ENET_RXD1__ENET_RX_DATA1
, ENET_PAD_CTRL
),
155 NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__ENET_RX_EN
, ENET_PAD_CTRL
),
156 NEW_PAD_CTRL(MX6_PAD_ENET_RX_ER__ENET_RX_ER
, ENET_PAD_CTRL
),
157 NEW_PAD_CTRL(MX6_PAD_ENET_TXD0__ENET_TX_DATA0
, ENET_PAD_CTRL
),
158 NEW_PAD_CTRL(MX6_PAD_ENET_TXD1__ENET_TX_DATA1
, ENET_PAD_CTRL
),
159 NEW_PAD_CTRL(MX6_PAD_ENET_TX_EN__ENET_TX_EN
, ENET_PAD_CTRL
),
160 NEW_PAD_CTRL(MX6_PAD_GPIO_19__ENET_TX_ER
, ENET_PAD_CTRL
),
163 NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08
, ENET_PAD_CTRL
),
164 /* ENET1 interrupt */
165 NEW_PAD_CTRL(MX6_PAD_GPIO_9__GPIO1_IO09
, ENET_PAD_CTRL
),
168 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 8)
170 static void setup_iomuxc_enet(void)
174 imx_iomux_v3_setup_multiple_pads(enet_pads
, ARRAY_SIZE(enet_pads
));
176 /* Reset LAN8720 PHY */
177 ret
= gpio_request(ENET_PHY_RESET_GPIO
, "phy-reset");
179 gpio_direction_output(ENET_PHY_RESET_GPIO
, 0);
181 gpio_set_value(ENET_PHY_RESET_GPIO
, 1);
184 int board_eth_init(bd_t
*bis
)
186 return cpu_eth_init(bis
);
190 #define GPIO_PAD_CTRL ( \
192 PAD_CTL_PUS_100K_UP | \
194 PAD_CTL_SPEED_MED | \
195 PAD_CTL_DSE_40ohm | \
199 #define GPIO_OD_PAD_CTRL ( \
201 PAD_CTL_PUS_100K_UP | \
204 PAD_CTL_SPEED_MED | \
205 PAD_CTL_DSE_40ohm | \
209 static iomux_v3_cfg_t
const gpio_pads
[] = {
211 NEW_PAD_CTRL(MX6_PAD_GPIO_0__GPIO1_IO00
, GPIO_PAD_CTRL
),
213 NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22
, GPIO_PAD_CTRL
),
215 NEW_PAD_CTRL(MX6_PAD_NANDF_CLE__GPIO6_IO07
, GPIO_OD_PAD_CTRL
),
217 NEW_PAD_CTRL(MX6_PAD_DISP0_DAT14__GPIO5_IO08
, GPIO_PAD_CTRL
),
219 NEW_PAD_CTRL(MX6_PAD_DISP0_DAT16__GPIO5_IO10
, GPIO_PAD_CTRL
),
221 NEW_PAD_CTRL(MX6_PAD_DISP0_DAT18__GPIO5_IO12
, GPIO_PAD_CTRL
),
224 #define GPIO_USB_H_PWR IMX_GPIO_NR(1, 0)
225 #define GPIO_USB_OTG_PWR IMX_GPIO_NR(3, 22)
226 #define GPIO_PCIE_RST IMX_GPIO_NR(6, 7)
227 #define GPIO_UART1_PWRON IMX_GPIO_NR(5, 8)
228 #define GPIO_UART2_PWRON IMX_GPIO_NR(5, 10)
229 #define GPIO_UART3_PWRON IMX_GPIO_NR(5, 12)
231 static void gpio_init(void)
235 imx_iomux_v3_setup_multiple_pads(gpio_pads
, ARRAY_SIZE(gpio_pads
));
237 ret
= gpio_request(GPIO_USB_H_PWR
, "usb-h-pwr");
239 gpio_direction_output(GPIO_USB_H_PWR
, 1);
240 ret
= gpio_request(GPIO_USB_OTG_PWR
, "usb-otg-pwr");
242 gpio_direction_output(GPIO_USB_OTG_PWR
, 1);
243 ret
= gpio_request(GPIO_PCIE_RST
, "pcie-reset");
245 gpio_direction_output(GPIO_PCIE_RST
, 1);
246 ret
= gpio_request(GPIO_UART1_PWRON
, "uart1-pwr");
248 gpio_direction_output(GPIO_UART1_PWRON
, 0);
249 ret
= gpio_request(GPIO_UART2_PWRON
, "uart2-pwr");
251 gpio_direction_output(GPIO_UART2_PWRON
, 0);
252 ret
= gpio_request(GPIO_UART3_PWRON
, "uart3-pwr");
254 gpio_direction_output(GPIO_UART3_PWRON
, 0);
257 void tqma6_iomuxc_spi(void)
259 /* No SPI on this baseboard */
262 int tqma6_bb_board_early_init_f(void)
264 setup_iomuxc_uart4();
269 int tqma6_bb_board_init(void)
275 /* Turn the UART-couplers on one-after-another */
276 gpio_set_value(GPIO_UART1_PWRON
, 1);
278 gpio_set_value(GPIO_UART2_PWRON
, 1);
280 gpio_set_value(GPIO_UART3_PWRON
, 1);
285 int tqma6_bb_board_late_init(void)
290 const char *tqma6_bb_get_boardname(void)
295 static const struct boot_mode board_boot_modes
[] = {
296 /* 4 bit bus width */
297 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
298 /* 8 bit bus width */
299 {"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
303 int misc_init_r(void)
305 add_board_boot_modes(board_boot_modes
);
310 #define WRU4_USB_H1_PWR IMX_GPIO_NR(1, 0)
311 #define WRU4_USB_OTG_PWR IMX_GPIO_NR(3, 22)
313 int board_ehci_hcd_init(int port
)
317 ret
= gpio_request(WRU4_USB_H1_PWR
, "usb-h1-pwr");
319 gpio_direction_output(WRU4_USB_H1_PWR
, 1);
321 ret
= gpio_request(WRU4_USB_OTG_PWR
, "usb-OTG-pwr");
323 gpio_direction_output(WRU4_USB_OTG_PWR
, 1);
328 int board_ehci_power(int port
, int on
)
331 gpio_set_value(WRU4_USB_OTG_PWR
, on
);
333 gpio_set_value(WRU4_USB_H1_PWR
, on
);
339 * Device Tree Support
341 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
342 void tqma6_bb_ft_board_setup(void *blob
, bd_t
*bd
)
346 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */