board/tqm5200/tqm5200.c

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * (C) Copyright 2004
   9  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <common.h>
  31 #include <mpc5xxx.h>
  32 #include <pci.h>
  33
  34 #if defined(CONFIG_MPC5200_DDR)
  35 #include "mt46v16m16-75.h"
  36 #else
  37 #include "mt48lc16m16a2-75.h"
  38 #endif
  39 #ifdef CONFIG_PS2MULT
  40 void ps2mult_early_init(void);
  41 #endif
  42
  43 #ifndef CFG_RAMBOOT
  44 static void sdram_start (int hi_addr)
  45 {
  46         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  47
  48         /* unlock mode register */
  49         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
  50                 hi_addr_bit;
  51         __asm__ volatile ("sync");
  52
  53         /* precharge all banks */
  54         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
  55                 hi_addr_bit;
  56         __asm__ volatile ("sync");
  57
  58 #if SDRAM_DDR
  59         /* set mode register: extended mode */
  60         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  61         __asm__ volatile ("sync");
  62
  63         /* set mode register: reset DLL */
  64         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  65         __asm__ volatile ("sync");
  66 #endif
  67
  68         /* precharge all banks */
  69         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
  70                 hi_addr_bit;
  71         __asm__ volatile ("sync");
  72
  73         /* auto refresh */
  74         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
  75                 hi_addr_bit;
  76         __asm__ volatile ("sync");
  77
  78         /* set mode register */
  79         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  80         __asm__ volatile ("sync");
  81
  82         /* normal operation */
  83         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  84         __asm__ volatile ("sync");
  85 }
  86 #endif
  87
  88 /*
  89  * ATTENTION: Although partially referenced initdram does NOT make real use
  90  *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
  91  *            is something else than 0x00000000.
  92  */
  93
  94 #if defined(CONFIG_MPC5200)
  95 long int initdram (int board_type)
  96 {
  97         ulong dramsize = 0;
  98         ulong dramsize2 = 0;
  99 #ifndef CFG_RAMBOOT
 100         ulong test1, test2;
 101
 102         /* setup SDRAM chip selects */
 103         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
 104         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
 105         __asm__ volatile ("sync");
 106
 107         /* setup config registers */
 108         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 109         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 110         __asm__ volatile ("sync");
 111
 112 #if SDRAM_DDR
 113         /* set tap delay */
 114         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 115         __asm__ volatile ("sync");
 116 #endif
 117
 118         /* find RAM size using SDRAM CS0 only */
 119         sdram_start(0);
 120         test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
 121         sdram_start(1);
 122         test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
 123         if (test1 > test2) {
 124                 sdram_start(0);
 125                 dramsize = test1;
 126         } else {
 127                 dramsize = test2;
 128         }
 129
 130         /* memory smaller than 1MB is impossible */
 131         if (dramsize < (1 << 20)) {
 132                 dramsize = 0;
 133         }
 134
 135         /* set SDRAM CS0 size according to the amount of RAM found */
 136         if (dramsize > 0) {
 137                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
 138                         __builtin_ffs(dramsize >> 20) - 1;
 139         } else {
 140                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 141         }
 142
 143         /* let SDRAM CS1 start right after CS0 */
 144         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
 145
 146         /* find RAM size using SDRAM CS1 only */
 147         sdram_start(0);
 148         test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
 149         sdram_start(1);
 150         test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
 151         if (test1 > test2) {
 152                 sdram_start(0);
 153                 dramsize2 = test1;
 154         } else {
 155                 dramsize2 = test2;
 156         }
 157
 158         /* memory smaller than 1MB is impossible */
 159         if (dramsize2 < (1 << 20)) {
 160                 dramsize2 = 0;
 161         }
 162
 163         /* set SDRAM CS1 size according to the amount of RAM found */
 164         if (dramsize2 > 0) {
 165                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 166                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 167         } else {
 168                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 169         }
 170
 171 #else /* CFG_RAMBOOT */
 172
 173         /* retrieve size of memory connected to SDRAM CS0 */
 174         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 175         if (dramsize >= 0x13) {
 176                 dramsize = (1 << (dramsize - 0x13)) << 20;
 177         } else {
 178                 dramsize = 0;
 179         }
 180
 181         /* retrieve size of memory connected to SDRAM CS1 */
 182         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 183         if (dramsize2 >= 0x13) {
 184                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 185         } else {
 186                 dramsize2 = 0;
 187         }
 188
 189 #endif /* CFG_RAMBOOT */
 190
 191 /*      return dramsize + dramsize2; */
 192         return dramsize;
 193 }
 194
 195 #elif defined(CONFIG_MGT5100)
 196
 197 long int initdram (int board_type)
 198 {
 199         ulong dramsize = 0;
 200 #ifndef CFG_RAMBOOT
 201         ulong test1, test2;
 202
 203         /* setup and enable SDRAM chip selects */
 204         *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
 205         *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
 206         *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
 207         __asm__ volatile ("sync");
 208
 209         /* setup config registers */
 210         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 211         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 212
 213         /* address select register */
 214         *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
 215         __asm__ volatile ("sync");
 216
 217         /* find RAM size */
 218         sdram_start(0);
 219         test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
 220         sdram_start(1);
 221         test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
 222         if (test1 > test2) {
 223                 sdram_start(0);
 224                 dramsize = test1;
 225         } else {
 226                 dramsize = test2;
 227         }
 228
 229         /* set SDRAM end address according to size */
 230         *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 231
 232 #else /* CFG_RAMBOOT */
 233
 234         /* Retrieve amount of SDRAM available */
 235         dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
 236
 237 #endif /* CFG_RAMBOOT */
 238
 239         return dramsize;
 240 }
 241
 242 #else
 243 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
 244 #endif
 245
 246 int checkboard (void)
 247 {
 248 #if defined (CONFIG_TQM5200_AA)
 249         puts ("Board: TQM5200-AA (TQ-Systems GmbH)\n");
 250 #elif defined (CONFIG_TQM5200_AB)
 251         puts ("Board: TQM5200-AB (TQ-Systems GmbH)\n");
 252 #elif defined (CONFIG_TQM5200_AC)
 253         puts ("Board: TQM5200-AC (TQ-Systems GmbH)\n");
 254 #elif defined (CONFIG_TQM5200)
 255         puts ("Board: TQM5200 (TQ-Systems GmbH)\n");
 256 #endif
 257 #if defined (CONFIG_STK52XX)
 258         puts ("       on a STK52XX baseboard\n");
 259 #endif
 260
 261         return 0;
 262 }
 263
 264 void flash_preinit(void)
 265 {
 266         /*
 267          * Now, when we are in RAM, enable flash write
 268          * access for detection process.
 269          * Note that CS_BOOT cannot be cleared when
 270          * executing in flash.
 271          */
 272 #if defined(CONFIG_MGT5100)
 273         *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
 274         *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
 275 #endif
 276         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 277 }
 278
 279
 280 #ifdef  CONFIG_PCI
 281 static struct pci_controller hose;
 282
 283 extern void pci_mpc5xxx_init(struct pci_controller *);
 284
 285 void pci_init_board(void)
 286 {
 287         pci_mpc5xxx_init(&hose);
 288 }
 289 #endif
 290
 291 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
 292
 293 #if defined (CONFIG_MINIFAP)
 294 #define SM501_POWER_MODE0_GATE          0x00000040UL
 295 #define SM501_POWER_MODE1_GATE          0x00000048UL
 296 #define POWER_MODE_GATE_GPIO_PWM_I2C    0x00000040UL
 297 #define SM501_GPIO_DATA_DIR_HIGH        0x0001000CUL
 298 #define SM501_GPIO_DATA_HIGH            0x00010004UL
 299 #define SM501_GPIO_51                   0x00080000UL
 300 #else
 301 #define GPIO_PSC1_4     0x01000000UL
 302 #endif
 303
 304 void init_ide_reset (void)
 305 {
 306         debug ("init_ide_reset\n");
 307
 308 #if defined (CONFIG_MINIFAP)
 309         /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
 310
 311         /* enable GPIO control (in both power modes) */
 312         *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
 313                 POWER_MODE_GATE_GPIO_PWM_I2C;
 314         *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
 315                 POWER_MODE_GATE_GPIO_PWM_I2C;
 316         /* configure GPIO51 as output */
 317         *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
 318                 SM501_GPIO_51;
 319 #else
 320         /* Configure PSC1_4 as GPIO output for ATA reset */
 321         *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 322         *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
 323 #endif
 324 }
 325
 326 void ide_set_reset (int idereset)
 327 {
 328         debug ("ide_reset(%d)\n", idereset);
 329
 330 #if defined (CONFIG_MINIFAP)
 331         if (idereset) {
 332                 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
 333                         ~SM501_GPIO_51;
 334         } else {
 335                 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
 336                         SM501_GPIO_51;
 337         }
 338 #else
 339         if (idereset) {
 340                 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
 341         } else {
 342                 *(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
 343         }
 344 #endif
 345 }
 346 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
 347
 348 #ifdef CONFIG_POST
 349 /*
 350  * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
 351  * is left open, no keypress is detected.
 352  */
 353 int post_hotkeys_pressed(void)
 354 {
 355         struct mpc5xxx_gpio *gpio;
 356
 357         gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
 358
 359         /*
 360          * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
 361          * CODEC or UART mode. Consumer IrDA should still be possible.
 362          */
 363         gpio->port_config &= ~(0x07000000);
 364         gpio->port_config |=   0x03000000;
 365
 366         /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
 367         gpio->simple_gpioe |= 0x20000000;
 368
 369         /* Configure GPIO_IRDA_1 as input */
 370         gpio->simple_ddr &= ~(0x20000000);
 371
 372         return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
 373 }
 374 #endif
 375
 376 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
 377
 378 void post_word_store (ulong a)
 379 {
 380         volatile ulong *save_addr =
 381                 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
 382
 383         *save_addr = a;
 384 }
 385
 386 ulong post_word_load (void)
 387 {
 388         volatile ulong *save_addr =
 389                 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
 390
 391         return *save_addr;
 392 }
 393 #endif  /* CONFIG_POST || CONFIG_LOGBUFFER*/
 394
 395 #ifdef CONFIG_PS2MULT
 396 #ifdef CONFIG_BOARD_EARLY_INIT_R
 397 int board_early_init_r (void)
 398 {
 399         ps2mult_early_init();
 400         return (0);
 401 }
 402 #endif
 403 #endif /* CONFIG_PS2MULT */
 404
 405 #if defined(CONFIG_CS_AUTOCONF)
 406 int last_stage_init (void)
 407 {
 408         /*
 409          * auto scan for really existing devices and re-set chip select
 410          * configuration.
 411          */
 412         u16 save, tmp;
 413         int restore;
 414
 415         /*
 416          * Check for SRAM and SRAM size
 417          */
 418
 419         /* save origianl SRAM content  */
 420         save = *(volatile u16 *)CFG_CS2_START;
 421         restore = 1;
 422
 423         /* write test pattern to SRAM */
 424         *(volatile u16 *)CFG_CS2_START = 0xA5A5;
 425         __asm__ volatile ("sync");
 426         /*
 427          * Put a different pattern on the data lines: otherwise they may float
 428          * long enough to read back what we wrote.
 429          */
 430         tmp = *(volatile u16 *)CFG_FLASH_BASE;
 431         if (tmp == 0xA5A5)
 432                 puts ("!! possible error in SRAM detection\n");
 433
 434         if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
 435                 /* no SRAM at all, disable cs */
 436                 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
 437                 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
 438                 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
 439                 restore = 0;
 440                 __asm__ volatile ("sync");
 441         }
 442         else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
 443                 /* make sure that we access a mirrored address */
 444                 *(volatile u16 *)CFG_CS2_START = 0x1111;
 445                 __asm__ volatile ("sync");
 446                 if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
 447                         /* SRAM size = 512 kByte */
 448                         *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
 449                                                                 0x80000);
 450                         __asm__ volatile ("sync");
 451                         puts ("SRAM:  512 kB\n");
 452                 }
 453                 else
 454                         puts ("!! possible error in SRAM detection\n");
 455         }
 456         else {
 457                 puts ("SRAM:  1 MB\n");
 458         }
 459         /* restore origianl SRAM content  */
 460         if (restore) {
 461                 *(volatile u16 *)CFG_CS2_START = save;
 462                 __asm__ volatile ("sync");
 463         }
 464
 465         /*
 466          * Check for Grafic Controller
 467          */
 468
 469         /* save origianl FB content  */
 470         save = *(volatile u16 *)CFG_CS1_START;
 471         restore = 1;
 472
 473         /* write test pattern to FB memory */
 474         *(volatile u16 *)CFG_CS1_START = 0xA5A5;
 475         __asm__ volatile ("sync");
 476         /*
 477          * Put a different pattern on the data lines: otherwise they may float
 478          * long enough to read back what we wrote.
 479          */
 480         tmp = *(volatile u16 *)CFG_FLASH_BASE;
 481         if (tmp == 0xA5A5)
 482                 puts ("!! possible error in grafic controller detection\n");
 483
 484         if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
 485                 /* no grafic controller at all, disable cs */
 486                 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
 487                 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
 488                 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
 489                 restore = 0;
 490                 __asm__ volatile ("sync");
 491         }
 492         else {
 493                 puts ("VGA:   SMI501 (Voyager) with 8 MB\n");
 494         }
 495         /* restore origianl FB content  */
 496         if (restore) {
 497                 *(volatile u16 *)CFG_CS1_START = save;
 498                 __asm__ volatile ("sync");
 499         }
 500
 501         return 0;
 502 }
 503 #endif /* CONFIG_CS_AUTOCONF */