board/tqm5200/tqm5200.c

   1 /*
   2  * (C) Copyright 2003-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * (C) Copyright 2004-2006
   9  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <common.h>
  31 #include <mpc5xxx.h>
  32 #include <pci.h>
  33 #include <asm/processor.h>
  34 #include <libfdt.h>
  35
  36 #ifdef CONFIG_VIDEO_SM501
  37 #include <sm501.h>
  38 #endif
  39
  40 #if defined(CONFIG_MPC5200_DDR)
  41 #include "mt46v16m16-75.h"
  42 #else
  43 #include "mt48lc16m16a2-75.h"
  44 #endif
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48 #ifdef CONFIG_PS2MULT
  49 void ps2mult_early_init(void);
  50 #endif
  51
  52 #ifndef CFG_RAMBOOT
  53 static void sdram_start (int hi_addr)
  54 {
  55         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  56
  57         /* unlock mode register */
  58         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
  59                 hi_addr_bit;
  60         __asm__ volatile ("sync");
  61
  62         /* precharge all banks */
  63         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
  64                 hi_addr_bit;
  65         __asm__ volatile ("sync");
  66
  67 #if SDRAM_DDR
  68         /* set mode register: extended mode */
  69         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  70         __asm__ volatile ("sync");
  71
  72         /* set mode register: reset DLL */
  73         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  74         __asm__ volatile ("sync");
  75 #endif
  76
  77         /* precharge all banks */
  78         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
  79                 hi_addr_bit;
  80         __asm__ volatile ("sync");
  81
  82         /* auto refresh */
  83         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
  84                 hi_addr_bit;
  85         __asm__ volatile ("sync");
  86
  87         /* set mode register */
  88         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  89         __asm__ volatile ("sync");
  90
  91         /* normal operation */
  92         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  93         __asm__ volatile ("sync");
  94 }
  95 #endif
  96
  97 /*
  98  * ATTENTION: Although partially referenced initdram does NOT make real use
  99  *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
 100  *            is something else than 0x00000000.
 101  */
 102
 103 #if defined(CONFIG_MPC5200)
 104 long int initdram (int board_type)
 105 {
 106         ulong dramsize = 0;
 107         ulong dramsize2 = 0;
 108         uint svr, pvr;
 109
 110 #ifndef CFG_RAMBOOT
 111         ulong test1, test2;
 112
 113         /* setup SDRAM chip selects */
 114         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
 115         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
 116         __asm__ volatile ("sync");
 117
 118         /* setup config registers */
 119         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 120         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 121         __asm__ volatile ("sync");
 122
 123 #if SDRAM_DDR
 124         /* set tap delay */
 125         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 126         __asm__ volatile ("sync");
 127 #endif
 128
 129         /* find RAM size using SDRAM CS0 only */
 130         sdram_start(0);
 131         test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
 132         sdram_start(1);
 133         test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
 134         if (test1 > test2) {
 135                 sdram_start(0);
 136                 dramsize = test1;
 137         } else {
 138                 dramsize = test2;
 139         }
 140
 141         /* memory smaller than 1MB is impossible */
 142         if (dramsize < (1 << 20)) {
 143                 dramsize = 0;
 144         }
 145
 146         /* set SDRAM CS0 size according to the amount of RAM found */
 147         if (dramsize > 0) {
 148                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
 149                         __builtin_ffs(dramsize >> 20) - 1;
 150         } else {
 151                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 152         }
 153
 154         /* let SDRAM CS1 start right after CS0 */
 155         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
 156
 157         /* find RAM size using SDRAM CS1 only */
 158         sdram_start(0);
 159         test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
 160         sdram_start(1);
 161         test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
 162         if (test1 > test2) {
 163                 sdram_start(0);
 164                 dramsize2 = test1;
 165         } else {
 166                 dramsize2 = test2;
 167         }
 168
 169         /* memory smaller than 1MB is impossible */
 170         if (dramsize2 < (1 << 20)) {
 171                 dramsize2 = 0;
 172         }
 173
 174         /* set SDRAM CS1 size according to the amount of RAM found */
 175         if (dramsize2 > 0) {
 176                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 177                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 178         } else {
 179                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 180         }
 181
 182 #else /* CFG_RAMBOOT */
 183
 184         /* retrieve size of memory connected to SDRAM CS0 */
 185         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 186         if (dramsize >= 0x13) {
 187                 dramsize = (1 << (dramsize - 0x13)) << 20;
 188         } else {
 189                 dramsize = 0;
 190         }
 191
 192         /* retrieve size of memory connected to SDRAM CS1 */
 193         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 194         if (dramsize2 >= 0x13) {
 195                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 196         } else {
 197                 dramsize2 = 0;
 198         }
 199 #endif /* CFG_RAMBOOT */
 200
 201         /*
 202          * On MPC5200B we need to set the special configuration delay in the
 203          * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
 204          * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
 205          *
 206          * "The SDelay should be written to a value of 0x00000004. It is
 207          * required to account for changes caused by normal wafer processing
 208          * parameters."
 209          */
 210         svr = get_svr();
 211         pvr = get_pvr();
 212         if ((SVR_MJREV(svr) >= 2) &&
 213             (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
 214
 215                 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
 216                 __asm__ volatile ("sync");
 217         }
 218
 219 #if defined(CONFIG_TQM5200_B)
 220         return dramsize + dramsize2;
 221 #else
 222         return dramsize;
 223 #endif /* CONFIG_TQM5200_B */
 224 }
 225
 226 #elif defined(CONFIG_MGT5100)
 227
 228 long int initdram (int board_type)
 229 {
 230         ulong dramsize = 0;
 231 #ifndef CFG_RAMBOOT
 232         ulong test1, test2;
 233
 234         /* setup and enable SDRAM chip selects */
 235         *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
 236         *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
 237         *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
 238         __asm__ volatile ("sync");
 239
 240         /* setup config registers */
 241         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 242         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 243
 244         /* address select register */
 245         *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
 246         __asm__ volatile ("sync");
 247
 248         /* find RAM size */
 249         sdram_start(0);
 250         test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
 251         sdram_start(1);
 252         test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
 253         if (test1 > test2) {
 254                 sdram_start(0);
 255                 dramsize = test1;
 256         } else {
 257                 dramsize = test2;
 258         }
 259
 260         /* set SDRAM end address according to size */
 261         *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 262
 263 #else /* CFG_RAMBOOT */
 264
 265         /* Retrieve amount of SDRAM available */
 266         dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
 267
 268 #endif /* CFG_RAMBOOT */
 269
 270         return dramsize;
 271 }
 272
 273 #else
 274 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
 275 #endif
 276
 277 int checkboard (void)
 278 {
 279 #if defined(CONFIG_AEVFIFO)
 280         puts ("Board: AEVFIFO\n");
 281         return 0;
 282 #endif
 283
 284 #if defined(CONFIG_TQM5200S)
 285 # define MODULE_NAME    "TQM5200S"
 286 #else
 287 # define MODULE_NAME    "TQM5200"
 288 #endif
 289
 290 #if defined(CONFIG_STK52XX)
 291 # define CARRIER_NAME   "STK52xx"
 292 #elif defined(CONFIG_TB5200)
 293 # define CARRIER_NAME   "TB5200"
 294 #elif defined(CONFIG_CAM5200)
 295 # define CARRIER_NAME   "CAM5200"
 296 #elif defined(CONFIG_FO300)
 297 # define CARRIER_NAME   "FO300"
 298 #else
 299 # error "UNKNOWN"
 300 #endif
 301
 302         puts (  "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
 303                 "       on a " CARRIER_NAME " carrier board\n");
 304
 305         return 0;
 306 }
 307
 308 #undef MODULE_NAME
 309 #undef CARRIER_NAME
 310
 311 void flash_preinit(void)
 312 {
 313         /*
 314          * Now, when we are in RAM, enable flash write
 315          * access for detection process.
 316          * Note that CS_BOOT cannot be cleared when
 317          * executing in flash.
 318          */
 319 #if defined(CONFIG_MGT5100)
 320         *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
 321         *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
 322 #endif
 323         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 324 }
 325
 326
 327 #ifdef  CONFIG_PCI
 328 static struct pci_controller hose;
 329
 330 extern void pci_mpc5xxx_init(struct pci_controller *);
 331
 332 void pci_init_board(void)
 333 {
 334         pci_mpc5xxx_init(&hose);
 335 }
 336 #endif
 337
 338 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 339
 340 #if defined (CONFIG_MINIFAP)
 341 #define SM501_POWER_MODE0_GATE          0x00000040UL
 342 #define SM501_POWER_MODE1_GATE          0x00000048UL
 343 #define POWER_MODE_GATE_GPIO_PWM_I2C    0x00000040UL
 344 #define SM501_GPIO_DATA_DIR_HIGH        0x0001000CUL
 345 #define SM501_GPIO_DATA_HIGH            0x00010004UL
 346 #define SM501_GPIO_51                   0x00080000UL
 347 #endif /* CONFIG MINIFAP */
 348
 349 void init_ide_reset (void)
 350 {
 351         debug ("init_ide_reset\n");
 352
 353 #if defined (CONFIG_MINIFAP)
 354         /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
 355
 356         /* enable GPIO control (in both power modes) */
 357         *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
 358                 POWER_MODE_GATE_GPIO_PWM_I2C;
 359         *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
 360                 POWER_MODE_GATE_GPIO_PWM_I2C;
 361         /* configure GPIO51 as output */
 362         *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
 363                 SM501_GPIO_51;
 364 #else
 365         /* Configure PSC1_4 as GPIO output for ATA reset */
 366         *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 367         *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
 368 #endif
 369 }
 370
 371 void ide_set_reset (int idereset)
 372 {
 373         debug ("ide_reset(%d)\n", idereset);
 374
 375 #if defined (CONFIG_MINIFAP)
 376         if (idereset) {
 377                 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
 378                         ~SM501_GPIO_51;
 379         } else {
 380                 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
 381                         SM501_GPIO_51;
 382         }
 383 #else
 384         if (idereset) {
 385                 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
 386         } else {
 387                 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
 388         }
 389 #endif
 390 }
 391 #endif
 392
 393 #ifdef CONFIG_POST
 394 /*
 395  * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
 396  * is left open, no keypress is detected.
 397  */
 398 int post_hotkeys_pressed(void)
 399 {
 400 #ifdef CONFIG_STK52XX
 401         struct mpc5xxx_gpio *gpio;
 402
 403         gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
 404
 405         /*
 406          * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
 407          * CODEC or UART mode. Consumer IrDA should still be possible.
 408          */
 409         gpio->port_config &= ~(0x07000000);
 410         gpio->port_config |=   0x03000000;
 411
 412         /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
 413         gpio->simple_gpioe |= 0x20000000;
 414
 415         /* Configure GPIO_IRDA_1 as input */
 416         gpio->simple_ddr &= ~(0x20000000);
 417
 418         return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
 419 #else
 420         return 0;
 421 #endif
 422 }
 423 #endif
 424
 425 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
 426
 427 void post_word_store (ulong a)
 428 {
 429         volatile ulong *save_addr =
 430                 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
 431
 432         *save_addr = a;
 433 }
 434
 435 ulong post_word_load (void)
 436 {
 437         volatile ulong *save_addr =
 438                 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
 439
 440         return *save_addr;
 441 }
 442 #endif  /* CONFIG_POST || CONFIG_LOGBUFFER*/
 443
 444 #ifdef CONFIG_PS2MULT
 445 #ifdef CONFIG_BOARD_EARLY_INIT_R
 446 int board_early_init_r (void)
 447 {
 448         ps2mult_early_init();
 449         return (0);
 450 }
 451 #endif
 452 #endif /* CONFIG_PS2MULT */
 453
 454 #ifdef CONFIG_FO300
 455 int silent_boot (void)
 456 {
 457         vu_long timer3_status;
 458
 459         /* Configure GPT3 as GPIO input */
 460         *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
 461
 462         /* Read in TIMER_3 pin status */
 463         timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
 464
 465 #ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
 466         /* Force silent console mode if S1 switch
 467          * is in closed position (TIMER_3 pin status is LOW). */
 468         if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
 469                 return 1;
 470 #else
 471         /* Force silent console mode if S1 switch
 472          * is in open position (TIMER_3 pin status is HIGH). */
 473         if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
 474                 return 1;
 475 #endif
 476
 477         return 0;
 478 }
 479
 480 int board_early_init_f (void)
 481 {
 482         if (silent_boot())
 483                 gd->flags |= GD_FLG_SILENT;
 484
 485         return 0;
 486 }
 487 #endif  /* CONFIG_FO300 */
 488
 489 int last_stage_init (void)
 490 {
 491         /*
 492          * auto scan for really existing devices and re-set chip select
 493          * configuration.
 494          */
 495         u16 save, tmp;
 496         int restore;
 497
 498         /*
 499          * Check for SRAM and SRAM size
 500          */
 501
 502         /* save original SRAM content  */
 503         save = *(volatile u16 *)CFG_CS2_START;
 504         restore = 1;
 505
 506         /* write test pattern to SRAM */
 507         *(volatile u16 *)CFG_CS2_START = 0xA5A5;
 508         __asm__ volatile ("sync");
 509         /*
 510          * Put a different pattern on the data lines: otherwise they may float
 511          * long enough to read back what we wrote.
 512          */
 513         tmp = *(volatile u16 *)CFG_FLASH_BASE;
 514         if (tmp == 0xA5A5)
 515                 puts ("!! possible error in SRAM detection\n");
 516
 517         if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
 518                 /* no SRAM at all, disable cs */
 519                 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
 520                 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
 521                 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
 522                 restore = 0;
 523                 __asm__ volatile ("sync");
 524         } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
 525                 /* make sure that we access a mirrored address */
 526                 *(volatile u16 *)CFG_CS2_START = 0x1111;
 527                 __asm__ volatile ("sync");
 528                 if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
 529                         /* SRAM size = 512 kByte */
 530                         *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
 531                                                                 0x80000);
 532                         __asm__ volatile ("sync");
 533                         puts ("SRAM:  512 kB\n");
 534                 }
 535                 else
 536                         puts ("!! possible error in SRAM detection\n");
 537         } else {
 538                 puts ("SRAM:  1 MB\n");
 539         }
 540         /* restore origianl SRAM content  */
 541         if (restore) {
 542                 *(volatile u16 *)CFG_CS2_START = save;
 543                 __asm__ volatile ("sync");
 544         }
 545
 546 #ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
 547         /*
 548          * Check for Grafic Controller
 549          */
 550
 551         /* save origianl FB content  */
 552         save = *(volatile u16 *)CFG_CS1_START;
 553         restore = 1;
 554
 555         /* write test pattern to FB memory */
 556         *(volatile u16 *)CFG_CS1_START = 0xA5A5;
 557         __asm__ volatile ("sync");
 558         /*
 559          * Put a different pattern on the data lines: otherwise they may float
 560          * long enough to read back what we wrote.
 561          */
 562         tmp = *(volatile u16 *)CFG_FLASH_BASE;
 563         if (tmp == 0xA5A5)
 564                 puts ("!! possible error in grafic controller detection\n");
 565
 566         if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
 567                 /* no grafic controller at all, disable cs */
 568                 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
 569                 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
 570                 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
 571                 restore = 0;
 572                 __asm__ volatile ("sync");
 573         } else {
 574                 puts ("VGA:   SMI501 (Voyager) with 8 MB\n");
 575         }
 576         /* restore origianl FB content  */
 577         if (restore) {
 578                 *(volatile u16 *)CFG_CS1_START = save;
 579                 __asm__ volatile ("sync");
 580         }
 581
 582 #ifdef CONFIG_FO300
 583         if (silent_boot()) {
 584                 setenv("bootdelay", "0");
 585                 disable_ctrlc(1);
 586         }
 587 #endif
 588
 589         return 0;
 590 #endif /* !CONFIG_TQM5200S */
 591 }
 592
 593 #ifdef CONFIG_VIDEO_SM501
 594
 595 #ifdef CONFIG_FO300
 596 #define DISPLAY_WIDTH   800
 597 #else
 598 #define DISPLAY_WIDTH   640
 599 #endif
 600 #define DISPLAY_HEIGHT  480
 601
 602 #ifdef CONFIG_VIDEO_SM501_8BPP
 603 #error CONFIG_VIDEO_SM501_8BPP not supported.
 604 #endif /* CONFIG_VIDEO_SM501_8BPP */
 605
 606 #ifdef CONFIG_VIDEO_SM501_16BPP
 607 #error CONFIG_VIDEO_SM501_16BPP not supported.
 608 #endif /* CONFIG_VIDEO_SM501_16BPP */
 609 #ifdef CONFIG_VIDEO_SM501_32BPP
 610 static const SMI_REGS init_regs [] =
 611 {
 612 #if 0 /* CRT only */
 613         {0x00004, 0x0},
 614         {0x00048, 0x00021807},
 615         {0x0004C, 0x10090a01},
 616         {0x00054, 0x1},
 617         {0x00040, 0x00021807},
 618         {0x00044, 0x10090a01},
 619         {0x00054, 0x0},
 620         {0x80200, 0x00010000},
 621         {0x80204, 0x0},
 622         {0x80208, 0x0A000A00},
 623         {0x8020C, 0x02fa027f},
 624         {0x80210, 0x004a028b},
 625         {0x80214, 0x020c01df},
 626         {0x80218, 0x000201e9},
 627         {0x80200, 0x00013306},
 628 #else  /* panel + CRT */
 629 #ifdef CONFIG_FO300
 630         {0x00004, 0x0},
 631         {0x00048, 0x00021807},
 632         {0x0004C, 0x301a0a01},
 633         {0x00054, 0x1},
 634         {0x00040, 0x00021807},
 635         {0x00044, 0x091a0a01},
 636         {0x00054, 0x0},
 637         {0x80000, 0x0f013106},
 638         {0x80004, 0xc428bb17},
 639         {0x8000C, 0x00000000},
 640         {0x80010, 0x0C800C80},
 641         {0x80014, 0x03200000},
 642         {0x80018, 0x01e00000},
 643         {0x8001C, 0x00000000},
 644         {0x80020, 0x01e00320},
 645         {0x80024, 0x042a031f},
 646         {0x80028, 0x0086034a},
 647         {0x8002C, 0x020c01df},
 648         {0x80030, 0x000201ea},
 649         {0x80200, 0x00010000},
 650 #else
 651         {0x00004, 0x0},
 652         {0x00048, 0x00021807},
 653         {0x0004C, 0x091a0a01},
 654         {0x00054, 0x1},
 655         {0x00040, 0x00021807},
 656         {0x00044, 0x091a0a01},
 657         {0x00054, 0x0},
 658         {0x80000, 0x0f013106},
 659         {0x80004, 0xc428bb17},
 660         {0x8000C, 0x00000000},
 661         {0x80010, 0x0a000a00},
 662         {0x80014, 0x02800000},
 663         {0x80018, 0x01e00000},
 664         {0x8001C, 0x00000000},
 665         {0x80020, 0x01e00280},
 666         {0x80024, 0x02fa027f},
 667         {0x80028, 0x004a028b},
 668         {0x8002C, 0x020c01df},
 669         {0x80030, 0x000201e9},
 670         {0x80200, 0x00010000},
 671 #endif /* #ifdef CONFIG_FO300 */
 672 #endif
 673         {0, 0}
 674 };
 675 #endif /* CONFIG_VIDEO_SM501_32BPP */
 676
 677 #ifdef CONFIG_CONSOLE_EXTRA_INFO
 678 /*
 679  * Return text to be printed besides the logo.
 680  */
 681 void video_get_info_str (int line_number, char *info)
 682 {
 683         if (line_number == 1) {
 684         strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
 685 #if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300)
 686         } else if (line_number == 2) {
 687 #if defined (CONFIG_STK52XX)
 688                 strcpy (info, "        on a STK52xx carrier board");
 689 #endif
 690 #if defined (CONFIG_TB5200)
 691                 strcpy (info, "        on a TB5200 carrier board");
 692 #endif
 693 #if defined (CONFIG_FO300)
 694                 strcpy (info, "        on a FO300 carrier board");
 695 #endif
 696 #endif
 697         }
 698         else {
 699                 info [0] = '\0';
 700         }
 701 }
 702 #endif
 703
 704 /*
 705  * Returns SM501 register base address. First thing called in the
 706  * driver. Checks if SM501 is physically present.
 707  */
 708 unsigned int board_video_init (void)
 709 {
 710         u16 save, tmp;
 711         int restore, ret;
 712
 713         /*
 714          * Check for Grafic Controller
 715          */
 716
 717         /* save origianl FB content  */
 718         save = *(volatile u16 *)CFG_CS1_START;
 719         restore = 1;
 720
 721         /* write test pattern to FB memory */
 722         *(volatile u16 *)CFG_CS1_START = 0xA5A5;
 723         __asm__ volatile ("sync");
 724         /*
 725          * Put a different pattern on the data lines: otherwise they may float
 726          * long enough to read back what we wrote.
 727          */
 728         tmp = *(volatile u16 *)CFG_FLASH_BASE;
 729         if (tmp == 0xA5A5)
 730                 puts ("!! possible error in grafic controller detection\n");
 731
 732         if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
 733                 /* no grafic controller found */
 734                 restore = 0;
 735                 ret = 0;
 736         } else {
 737                 ret = SM501_MMIO_BASE;
 738         }
 739
 740         if (restore) {
 741                 *(volatile u16 *)CFG_CS1_START = save;
 742                 __asm__ volatile ("sync");
 743         }
 744         return ret;
 745 }
 746
 747 /*
 748  * Returns SM501 framebuffer address
 749  */
 750 unsigned int board_video_get_fb (void)
 751 {
 752         return SM501_FB_BASE;
 753 }
 754
 755 /*
 756  * Called after initializing the SM501 and before clearing the screen.
 757  */
 758 void board_validate_screen (unsigned int base)
 759 {
 760 }
 761
 762 /*
 763  * Return a pointer to the initialization sequence.
 764  */
 765 const SMI_REGS *board_get_regs (void)
 766 {
 767         return init_regs;
 768 }
 769
 770 int board_get_width (void)
 771 {
 772         return DISPLAY_WIDTH;
 773 }
 774
 775 int board_get_height (void)
 776 {
 777         return DISPLAY_HEIGHT;
 778 }
 779
 780 #endif /* CONFIG_VIDEO_SM501 */
 781
 782 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 783 void ft_board_setup(void *blob, bd_t *bd)
 784 {
 785         ft_cpu_setup(blob, bd);
 786 }
 787 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */