board/trizepsiv/conxs.c

   1 /*
   2  * (C) Copyright 2007
   3  * Stefano Babic, DENX Gmbh, sbabic@denx.de
   4  *
   5  * (C) Copyright 2004
   6  * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
   7  *
   8  * (C) Copyright 2002
   9  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  10  *
  11  * (C) Copyright 2002
  12  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  13  * Marius Groeger <mgroeger@sysgo.de>
  14  *
  15  * SPDX-License-Identifier:     GPL-2.0+
  16  */
  17
  18 #include <common.h>
  19 #include <asm/arch/pxa-regs.h>
  20 #include <asm/arch/pxa.h>
  21 #include <asm/arch/regs-mmc.h>
  22 #include <netdev.h>
  23 #include <asm/io.h>
  24 #include <usb.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #define         RH_A_PSM        (1 << 8)        /* power switching mode */
  29 #define         RH_A_NPS        (1 << 9)        /* no power switching */
  30
  31 extern struct serial_device serial_ffuart_device;
  32 extern struct serial_device serial_btuart_device;
  33 extern struct serial_device serial_stuart_device;
  34
  35 #if CONFIG_MK_POLARIS
  36 #define BOOT_CONSOLE    "serial_stuart"
  37 #else
  38 #define BOOT_CONSOLE    "serial_ffuart"
  39 #endif
  40 /* ------------------------------------------------------------------------- */
  41
  42 /*
  43  * Miscelaneous platform dependent initialisations
  44  */
  45
  46 int board_usb_init(int index, enum usb_init_type init)
  47 {
  48         writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
  49                 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
  50                 UHCHR);
  51
  52         writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  53
  54         while (readl(UHCHR) & UHCHR_FSBIR)
  55                 ;
  56
  57         writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
  58         writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
  59
  60         /* Clear any OTG Pin Hold */
  61         if (readl(PSSR) & PSSR_OTGPH)
  62                 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
  63
  64         writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
  65         writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
  66
  67         /* Set port power control mask bits, only 3 ports. */
  68         writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
  69
  70         return 0;
  71 }
  72
  73 int board_usb_cleanup(int index, enum usb_init_type init)
  74 {
  75         return 0;
  76 }
  77
  78 void usb_board_stop(void)
  79 {
  80         writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
  81         udelay(11);
  82         writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
  83
  84         writel(readl(UHCCOMS) | 1, UHCCOMS);
  85         udelay(10);
  86
  87         writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
  88
  89         return;
  90 }
  91
  92 int board_init (void)
  93 {
  94         /* We have RAM, disable cache */
  95         dcache_disable();
  96         icache_disable();
  97
  98         /* arch number of ConXS Board */
  99         gd->bd->bi_arch_number = 776;
 100
 101         /* adress of boot parameters */
 102         gd->bd->bi_boot_params = 0xa000003c;
 103
 104         return 0;
 105 }
 106
 107 int board_late_init(void)
 108 {
 109         char *console=getenv("boot_console");
 110
 111         if ((console == NULL) || (strcmp(console,"serial_btuart") &&
 112                 strcmp(console,"serial_stuart") &&
 113                 strcmp(console,"serial_ffuart"))) {
 114                         console = BOOT_CONSOLE;
 115         }
 116         setenv("stdout",console);
 117         setenv("stdin", console);
 118         setenv("stderr",console);
 119         return 0;
 120 }
 121
 122 int dram_init(void)
 123 {
 124         pxa2xx_dram_init();
 125         gd->ram_size = PHYS_SDRAM_1_SIZE;
 126         return 0;
 127 }
 128
 129 void dram_init_banksize(void)
 130 {
 131         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 132         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 133 }
 134
 135 #ifdef CONFIG_DRIVER_DM9000
 136 int board_eth_init(bd_t *bis)
 137 {
 138         return dm9000_initialize(bis);
 139 }
 140 #endif
 141
 142 #ifdef CONFIG_CMD_MMC
 143 int board_mmc_init(bd_t *bis)
 144 {
 145         pxa_mmc_register(0);
 146         return 0;
 147 }
 148 #endif