2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <linux/errno.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/sata.h>
19 #include <fsl_esdhc.h>
20 #include <asm/arch/crm_regs.h>
22 #include <asm/arch/sys_proto.h>
27 DECLARE_GLOBAL_DATA_PTR
;
29 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
30 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
31 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
33 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
34 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
37 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
38 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40 #define WDT_EN IMX_GPIO_NR(5, 4)
41 #define WDT_TRG IMX_GPIO_NR(3, 19)
45 gd
->ram_size
= imx_ddr_size();
50 static iomux_v3_cfg_t
const uart2_pads
[] = {
51 IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
52 IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
55 static iomux_v3_cfg_t
const usdhc3_pads
[] = {
56 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
57 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
58 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
59 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
60 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
61 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
64 static iomux_v3_cfg_t
const wdog_pads
[] = {
65 IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
66 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19
),
69 int mx6_rgmii_rework(struct phy_device
*phydev
)
72 * Bug: Apparently uDoo does not works with Gigabit switches...
73 * Limiting speed to 10/100Mbps, and setting master mode, seems to
74 * be the only way to have a successfull PHY auto negotiation.
75 * How to fix: Understand why Linux kernel do not have this issue.
77 phy_write(phydev
, MDIO_DEVAD_NONE
, MII_CTRL1000
, 0x1c00);
79 /* control data pad skew - devaddr = 0x02, register = 0x04 */
80 ksz9031_phy_extended_write(phydev
, 0x02,
81 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW
,
82 MII_KSZ9031_MOD_DATA_NO_POST_INC
, 0x0000);
83 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
84 ksz9031_phy_extended_write(phydev
, 0x02,
85 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW
,
86 MII_KSZ9031_MOD_DATA_NO_POST_INC
, 0x0000);
87 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
88 ksz9031_phy_extended_write(phydev
, 0x02,
89 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW
,
90 MII_KSZ9031_MOD_DATA_NO_POST_INC
, 0x0000);
91 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
92 ksz9031_phy_extended_write(phydev
, 0x02,
93 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW
,
94 MII_KSZ9031_MOD_DATA_NO_POST_INC
, 0x03FF);
98 static iomux_v3_cfg_t
const enet_pads1
[] = {
99 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
100 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
101 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
102 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
103 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
104 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
105 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
106 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
107 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
108 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
110 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
111 /* Ethernet power supply */
112 IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
113 /* pin 32 - 1 - (MODE0) all */
114 IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
115 /* pin 31 - 1 - (MODE1) all */
116 IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
117 /* pin 28 - 1 - (MODE2) all */
118 IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
119 /* pin 27 - 1 - (MODE3) all */
120 IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
121 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
122 IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
125 static iomux_v3_cfg_t
const enet_pads2
[] = {
126 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
127 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
128 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
129 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
130 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
133 static void setup_iomux_enet(void)
135 SETUP_IOMUX_PADS(enet_pads1
);
137 gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
139 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
141 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
142 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
143 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
144 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
145 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
148 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
150 /* Need 100ms delay to exit from reset. */
153 gpio_free(IMX_GPIO_NR(6, 24));
154 gpio_free(IMX_GPIO_NR(6, 25));
155 gpio_free(IMX_GPIO_NR(6, 27));
156 gpio_free(IMX_GPIO_NR(6, 28));
157 gpio_free(IMX_GPIO_NR(6, 29));
159 SETUP_IOMUX_PADS(enet_pads2
);
162 static void setup_iomux_uart(void)
164 SETUP_IOMUX_PADS(uart2_pads
);
167 static void setup_iomux_wdog(void)
169 SETUP_IOMUX_PADS(wdog_pads
);
170 gpio_direction_output(WDT_TRG
, 0);
171 gpio_direction_output(WDT_EN
, 1);
172 gpio_direction_input(WDT_TRG
);
175 static struct fsl_esdhc_cfg usdhc_cfg
= { USDHC3_BASE_ADDR
};
177 int board_mmc_getcd(struct mmc
*mmc
)
179 return 1; /* Always present */
182 int board_eth_init(bd_t
*bis
)
184 uint32_t base
= IMX_FEC_BASE
;
185 struct mii_dev
*bus
= NULL
;
186 struct phy_device
*phydev
= NULL
;
191 #ifdef CONFIG_FEC_MXC
192 bus
= fec_get_miibus(base
, -1);
195 /* scan phy 4,5,6,7 */
196 phydev
= phy_find_by_mask(bus
, (0xf << 4), PHY_INTERFACE_MODE_RGMII
);
202 printf("using phy at %d\n", phydev
->addr
);
203 ret
= fec_probe(bis
, -1, base
, bus
, phydev
);
216 int board_mmc_init(bd_t
*bis
)
218 SETUP_IOMUX_PADS(usdhc3_pads
);
219 usdhc_cfg
.sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
220 usdhc_cfg
.max_bus_width
= 4;
222 return fsl_esdhc_initialize(bis
, &usdhc_cfg
);
225 int board_early_init_f(void)
233 int board_phy_config(struct phy_device
*phydev
)
235 mx6_rgmii_rework(phydev
);
236 if (phydev
->drv
->config
)
237 phydev
->drv
->config(phydev
);
244 /* address of boot parameters */
245 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
253 int board_late_init(void)
255 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
256 if (is_cpu_type(MXC_CPU_MX6Q
))
257 env_set("board_rev", "MX6Q");
259 env_set("board_rev", "MX6DL");
266 if (is_cpu_type(MXC_CPU_MX6Q
))
267 puts("Board: Udoo Quad\n");
269 puts("Board: Udoo DualLite\n");