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git.ipfire.org Git - people/ms/u-boot.git/blob - board/v38b/v38b.c
2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
32 #ifndef CONFIG_SYS_RAMBOOT
33 static void sdram_start(int hi_addr
)
35 long hi_addr_bit
= hi_addr
? 0x01000000 : 0;
37 /* unlock mode register */
38 *(vu_long
*) MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000000 | hi_addr_bit
;
39 __asm__
volatile ("sync");
41 /* precharge all banks */
42 *(vu_long
*) MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000002 | hi_addr_bit
;
43 __asm__
volatile ("sync");
46 /* set mode register: extended mode */
47 *(vu_long
*) MPC5XXX_SDRAM_MODE
= SDRAM_EMODE
;
48 __asm__
volatile ("sync");
50 /* set mode register: reset DLL */
51 *(vu_long
*) MPC5XXX_SDRAM_MODE
= SDRAM_MODE
| 0x04000000;
52 __asm__
volatile ("sync");
53 #endif /* SDRAM_DDR */
55 /* precharge all banks */
56 *(vu_long
*) MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000002 | hi_addr_bit
;
57 __asm__
volatile ("sync");
60 *(vu_long
*) MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000004 | hi_addr_bit
;
61 __asm__
volatile ("sync");
63 /* set mode register */
64 *(vu_long
*) MPC5XXX_SDRAM_MODE
= SDRAM_MODE
;
65 __asm__
volatile ("sync");
67 /* normal operation */
68 *(vu_long
*) MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| hi_addr_bit
;
69 __asm__
volatile ("sync");
71 #endif /* !CONFIG_SYS_RAMBOOT */
74 phys_size_t
initdram(int board_type
)
80 #ifndef CONFIG_SYS_RAMBOOT
83 /* setup SDRAM chip selects */
84 *(vu_long
*) MPC5XXX_SDRAM_CS0CFG
= 0x0000001e; /* 2G at 0x0 */
85 *(vu_long
*) MPC5XXX_SDRAM_CS1CFG
= 0x80000000; /* disabled */
86 __asm__
volatile ("sync");
88 /* setup config registers */
89 *(vu_long
*) MPC5XXX_SDRAM_CONFIG1
= SDRAM_CONFIG1
;
90 *(vu_long
*) MPC5XXX_SDRAM_CONFIG2
= SDRAM_CONFIG2
;
91 __asm__
volatile ("sync");
95 *(vu_long
*) MPC5XXX_CDM_PORCFG
= SDRAM_TAPDELAY
;
96 __asm__
volatile ("sync");
97 #endif /* SDRAM_DDR */
99 /* find RAM size using SDRAM CS0 only */
101 test1
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x80000000);
103 test2
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x80000000);
110 /* memory smaller than 1MB is impossible */
111 if (dramsize
< (1 << 20))
114 /* set SDRAM CS0 size according to the amount of RAM found */
116 *(vu_long
*) MPC5XXX_SDRAM_CS0CFG
= 0x13 + __builtin_ffs(dramsize
>> 20) - 1;
118 *(vu_long
*) MPC5XXX_SDRAM_CS0CFG
= 0; /* disabled */
120 /* let SDRAM CS1 start right after CS0 */
121 *(vu_long
*) MPC5XXX_SDRAM_CS1CFG
= dramsize
+ 0x0000001e;/* 2G */
123 /* find RAM size using SDRAM CS1 only */
126 test2
= test1
= get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE
+ dramsize
), 0x80000000);
129 test2
= get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE
+ dramsize
), 0x80000000);
137 /* memory smaller than 1MB is impossible */
138 if (dramsize2
< (1 << 20))
141 /* set SDRAM CS1 size according to the amount of RAM found */
143 *(vu_long
*) MPC5XXX_SDRAM_CS1CFG
= dramsize
144 | (0x13 + __builtin_ffs(dramsize2
>> 20) - 1);
146 *(vu_long
*) MPC5XXX_SDRAM_CS1CFG
= dramsize
; /* disabled */
148 #else /* CONFIG_SYS_RAMBOOT */
150 /* retrieve size of memory connected to SDRAM CS0 */
151 dramsize
= *(vu_long
*) MPC5XXX_SDRAM_CS0CFG
& 0xFF;
152 if (dramsize
>= 0x13)
153 dramsize
= (1 << (dramsize
- 0x13)) << 20;
157 /* retrieve size of memory connected to SDRAM CS1 */
158 dramsize2
= *(vu_long
*) MPC5XXX_SDRAM_CS1CFG
& 0xFF;
159 if (dramsize2
>= 0x13)
160 dramsize2
= (1 << (dramsize2
- 0x13)) << 20;
164 #endif /* CONFIG_SYS_RAMBOOT */
167 * On MPC5200B we need to set the special configuration delay in the
168 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
169 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
171 * "The SDelay should be written to a value of 0x00000004. It is
172 * required to account for changes caused by normal wafer processing
177 if ((SVR_MJREV(svr
) >= 2) &&
178 (PVR_MAJ(pvr
) == 1) && (PVR_MIN(pvr
) == 4)) {
180 *(vu_long
*) MPC5XXX_SDRAM_SDELAY
= 0x04;
181 __asm__
volatile ("sync");
184 return dramsize
+ dramsize2
;
188 int checkboard (void)
190 puts("Board: MarelV38B\n");
194 int board_early_init_f(void)
196 #ifdef CONFIG_HW_WATCHDOG
198 * Enable and configure the direction (output) of PSC3_9 - watchdog
199 * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
202 *(vu_long
*) MPC5XXX_WU_GPIO_ENABLE
|= GPIO_PSC3_9
;
203 *(vu_long
*) MPC5XXX_WU_GPIO_DIR
|= GPIO_PSC3_9
;
204 #endif /* CONFIG_HW_WATCHDOG */
208 int board_early_init_r(void)
211 * Now, when we are in RAM, enable flash write access for the
212 * detection process. Note that CS_BOOT cannot be cleared when
213 * executing in flash.
215 *(vu_long
*) MPC5XXX_BOOTCS_CFG
&= ~0x1; /* clear RO */
218 * Enable GPIO_WKUP_7 to "read the status of the actual power
219 * situation". Default direction is input, so no need to set it
222 *(vu_long
*) MPC5XXX_WU_GPIO_ENABLE
|= GPIO_WKUP_7
;
227 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
228 void init_ide_reset(void)
230 debug("init_ide_reset\n");
232 /* Configure PSC1_4 as GPIO output for ATA reset */
233 *(vu_long
*) MPC5XXX_WU_GPIO_ENABLE
|= GPIO_PSC1_4
;
234 *(vu_long
*) MPC5XXX_WU_GPIO_DIR
|= GPIO_PSC1_4
;
236 *(vu_long
*) MPC5XXX_WU_GPIO_DATA_O
|= GPIO_PSC1_4
;
240 void ide_set_reset(int idereset
)
242 debug("ide_reset(%d)\n", idereset
);
245 *(vu_long
*) MPC5XXX_WU_GPIO_DATA_O
&= ~GPIO_PSC1_4
;
246 /* Make a delay. MPC5200 spec says 25 usec min */
249 *(vu_long
*) MPC5XXX_WU_GPIO_DATA_O
|= GPIO_PSC1_4
;
254 #ifdef CONFIG_HW_WATCHDOG
255 void hw_watchdog_reset(void)
258 * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
259 * we need a positive or negative transition on WDI i.e., our PSC3_9.
261 *(vu_long
*) MPC5XXX_WU_GPIO_DATA_O
^= GPIO_PSC3_9
;
263 #endif /* CONFIG_HW_WATCHDOG */