3 * Based somewhat on board/freescale/corenet_ds/eth_hydra.c
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/fsl_serdes.h>
14 #include <fdt_support.h>
15 #include <fsl_dtsec.h>
17 #ifdef CONFIG_FMAN_ENET
19 #define FIRST_PORT_ADDR 3
20 #define SECOND_PORT_ADDR 7
22 #ifdef CONFIG_ARCH_P5040
23 #define FIRST_PORT FM1_DTSEC5
24 #define SECOND_PORT FM2_DTSEC5
26 #define FIRST_PORT FM1_DTSEC4
27 #define SECOND_PORT FM1_DTSEC5
30 #define IS_VALID_PORT(p) ((p) == FIRST_PORT || (p) == SECOND_PORT)
32 static void cyrus_phy_tuning(int phy
)
35 * Enable RGMII delay on Tx and Rx for CPU port
37 printf("Tuning PHY @ %d\n", phy
);
39 /* sets address 0x104 or reg 260 for writing */
40 miiphy_write(DEFAULT_FM_MDIO_NAME
, phy
, 0xb, 0x8104);
41 /* Sets RXC/TXC to +0.96ns and TX_CTL/RX_CTL to -0.84ns */
42 miiphy_write(DEFAULT_FM_MDIO_NAME
, phy
, 0xc, 0xf0f0);
43 /* sets address 0x105 or reg 261 for writing */
44 miiphy_write(DEFAULT_FM_MDIO_NAME
, phy
, 0xb, 0x8105);
45 /* writes to address 0x105 , RXD[3..0] to -0. */
46 miiphy_write(DEFAULT_FM_MDIO_NAME
, phy
, 0xc, 0x0000);
47 /* sets address 0x106 or reg 261 for writing */
48 miiphy_write(DEFAULT_FM_MDIO_NAME
, phy
, 0xb, 0x8106);
49 /* writes to address 0x106 , TXD[3..0] to -0.84ns */
50 miiphy_write(DEFAULT_FM_MDIO_NAME
, phy
, 0xc, 0x0000);
51 /* force re-negotiation */
52 miiphy_write(DEFAULT_FM_MDIO_NAME
, phy
, 0x0, 0x1340);
56 int board_eth_init(bd_t
*bis
)
58 #ifdef CONFIG_FMAN_ENET
59 struct fsl_pq_mdio_info dtsec_mdio_info
;
62 printf("Initializing Fman\n");
65 /* Register the real 1G MDIO bus */
66 dtsec_mdio_info
.regs
=
67 (struct tsec_mii_mng
*)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR
;
68 dtsec_mdio_info
.name
= DEFAULT_FM_MDIO_NAME
;
70 fsl_pq_mdio_init(bis
, &dtsec_mdio_info
);
73 fm_info_set_phy_address(FIRST_PORT
, FIRST_PORT_ADDR
);
74 fm_info_set_mdio(FIRST_PORT
,
75 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME
));
76 fm_info_set_phy_address(SECOND_PORT
, SECOND_PORT_ADDR
);
77 fm_info_set_mdio(SECOND_PORT
,
78 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME
));
80 /* Never disable DTSEC1 - it controls MDIO */
81 for (i
= FM1_DTSEC2
; i
< FM1_DTSEC1
+ CONFIG_SYS_NUM_FM1_DTSEC
; i
++) {
82 if (!IS_VALID_PORT(i
))
86 #ifdef CONFIG_ARCH_P5040
87 for (i
= FM2_DTSEC2
; i
< FM2_DTSEC1
+ CONFIG_SYS_NUM_FM2_DTSEC
; i
++) {
88 if (!IS_VALID_PORT(i
))
95 cyrus_phy_tuning(FIRST_PORT_ADDR
);
96 cyrus_phy_tuning(SECOND_PORT_ADDR
);
99 return pci_eth_init(bis
);