board/vscom/baltos/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for TI AM335X based boards
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <errno.h>
  13 #include <init.h>
  14 #include <serial.h>
  15 #include <linux/libfdt.h>
  16 #include <spl.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/hardware.h>
  19 #include <asm/arch/omap.h>
  20 #include <asm/arch/ddr_defs.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <asm/arch/mem.h>
  26 #include <asm/arch/mux.h>
  27 #include <asm/io.h>
  28 #include <asm/emif.h>
  29 #include <asm/gpio.h>
  30 #include <i2c.h>
  31 #include <miiphy.h>
  32 #include <cpsw.h>
  33 #include <power/tps65910.h>
  34 #include <watchdog.h>
  35 #include "board.h"
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 /* GPIO that controls DIP switch and mPCIe slot */
  40 #define DIP_S1                  44
  41 #define MPCIE_SW                100
  42
  43 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  44
  45 static int baltos_set_console(void)
  46 {
  47         int val, i, dips = 0;
  48         char buf[7];
  49
  50         for (i = 0; i < 4; i++) {
  51                 sprintf(buf, "dip_s%d", i + 1);
  52
  53                 if (gpio_request(DIP_S1 + i, buf)) {
  54                         printf("failed to export GPIO %d\n", DIP_S1 + i);
  55                         return 0;
  56                 }
  57
  58                 if (gpio_direction_input(DIP_S1 + i)) {
  59                         printf("failed to set GPIO %d direction\n", DIP_S1 + i);
  60                         return 0;
  61                 }
  62
  63                 val = gpio_get_value(DIP_S1 + i);
  64                 dips |= val << i;
  65         }
  66
  67         printf("DIPs: 0x%1x\n", (~dips) & 0xf);
  68
  69         if ((dips & 0xf) == 0xe)
  70                 env_set("console", "ttyUSB0,115200n8");
  71
  72         return 0;
  73 }
  74
  75 static int read_eeprom(BSP_VS_HWPARAM *header)
  76 {
  77         i2c_set_bus_num(1);
  78
  79         /* Check if baseboard eeprom is available */
  80         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  81                 puts("Could not probe the EEPROM; something fundamentally "
  82                         "wrong on the I2C bus.\n");
  83                 return -ENODEV;
  84         }
  85
  86         /* read the eeprom using i2c */
  87         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  88                      sizeof(BSP_VS_HWPARAM))) {
  89                 puts("Could not read the EEPROM; something fundamentally"
  90                         " wrong on the I2C bus.\n");
  91                 return -EIO;
  92         }
  93
  94         if (header->Magic != 0xDEADBEEF) {
  95
  96                 printf("Incorrect magic number (0x%x) in EEPROM\n",
  97                                 header->Magic);
  98
  99                 /* fill default values */
 100                 header->SystemId = 211;
 101                 header->MAC1[0] = 0x00;
 102                 header->MAC1[1] = 0x00;
 103                 header->MAC1[2] = 0x00;
 104                 header->MAC1[3] = 0x00;
 105                 header->MAC1[4] = 0x00;
 106                 header->MAC1[5] = 0x01;
 107
 108                 header->MAC2[0] = 0x00;
 109                 header->MAC2[1] = 0x00;
 110                 header->MAC2[2] = 0x00;
 111                 header->MAC2[3] = 0x00;
 112                 header->MAC2[4] = 0x00;
 113                 header->MAC2[5] = 0x02;
 114
 115                 header->MAC3[0] = 0x00;
 116                 header->MAC3[1] = 0x00;
 117                 header->MAC3[2] = 0x00;
 118                 header->MAC3[3] = 0x00;
 119                 header->MAC3[4] = 0x00;
 120                 header->MAC3[5] = 0x03;
 121         }
 122
 123         return 0;
 124 }
 125
 126 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
 127
 128 static const struct ddr_data ddr3_baltos_data = {
 129         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 130         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 131         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 132         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 133 };
 134
 135 static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
 136         .cmd0csratio = MT41K256M16HA125E_RATIO,
 137         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 138
 139         .cmd1csratio = MT41K256M16HA125E_RATIO,
 140         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 141
 142         .cmd2csratio = MT41K256M16HA125E_RATIO,
 143         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 144 };
 145
 146 static struct emif_regs ddr3_baltos_emif_reg_data = {
 147         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 148         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 149         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 150         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 151         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 152         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 153         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 154 };
 155
 156 #ifdef CONFIG_SPL_OS_BOOT
 157 int spl_start_uboot(void)
 158 {
 159         /* break into full u-boot on 'c' */
 160         return (serial_tstc() && serial_getc() == 'c');
 161 }
 162 #endif
 163
 164 #define OSC     (V_OSCK/1000000)
 165 const struct dpll_params dpll_ddr = {
 166                 266, OSC-1, 1, -1, -1, -1, -1};
 167 const struct dpll_params dpll_ddr_evm_sk = {
 168                 303, OSC-1, 1, -1, -1, -1, -1};
 169 const struct dpll_params dpll_ddr_baltos = {
 170                 400, OSC-1, 1, -1, -1, -1, -1};
 171
 172 void am33xx_spl_board_init(void)
 173 {
 174         int mpu_vdd;
 175         int sil_rev;
 176
 177         /* Get the frequency */
 178         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 179
 180         /*
 181          * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 182          * MPU frequencies we support we use a CORE voltage of
 183          * 1.1375V.  For MPU voltage we need to switch based on
 184          * the frequency we are running at.
 185          */
 186         i2c_set_bus_num(1);
 187
 188         printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
 189
 190         if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
 191                 puts("i2c: cannot access TPS65910\n");
 192                 return;
 193         }
 194
 195         /*
 196          * Depending on MPU clock and PG we will need a different
 197          * VDD to drive at that speed.
 198          */
 199         sil_rev = readl(&cdev->deviceid) >> 28;
 200         mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
 201                                               dpll_mpu_opp100.m);
 202
 203         /* Tell the TPS65910 to use i2c */
 204         tps65910_set_i2c_control();
 205
 206         /* First update MPU voltage. */
 207         if (tps65910_voltage_update(MPU, mpu_vdd))
 208                 return;
 209
 210         /* Second, update the CORE voltage. */
 211         if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
 212                 return;
 213
 214         /* Set CORE Frequencies to OPP100 */
 215         do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 216
 217         /* Set MPU Frequency to what we detected now that voltages are set */
 218         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 219
 220         writel(0x000010ff, PRM_DEVICE_INST + 4);
 221 }
 222
 223 const struct dpll_params *get_dpll_ddr_params(void)
 224 {
 225         enable_i2c1_pin_mux();
 226         i2c_set_bus_num(1);
 227
 228         return &dpll_ddr_baltos;
 229 }
 230
 231 void set_uart_mux_conf(void)
 232 {
 233         enable_uart0_pin_mux();
 234 }
 235
 236 void set_mux_conf_regs(void)
 237 {
 238         enable_board_pin_mux();
 239 }
 240
 241 const struct ctrl_ioregs ioregs_baltos = {
 242         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 243         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 244         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 245         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 246         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 247 };
 248
 249 void sdram_init(void)
 250 {
 251         config_ddr(400, &ioregs_baltos,
 252                    &ddr3_baltos_data,
 253                    &ddr3_baltos_cmd_ctrl_data,
 254                    &ddr3_baltos_emif_reg_data, 0);
 255 }
 256 #endif
 257
 258 /*
 259  * Basic board specific setup.  Pinmux has been handled already.
 260  */
 261 int board_init(void)
 262 {
 263 #if defined(CONFIG_HW_WATCHDOG)
 264         hw_watchdog_init();
 265 #endif
 266
 267         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 268 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
 269         gpmc_init();
 270 #endif
 271         return 0;
 272 }
 273
 274 int ft_board_setup(void *blob, bd_t *bd)
 275 {
 276         int node, ret;
 277         unsigned char mac_addr[6];
 278         BSP_VS_HWPARAM header;
 279
 280         /* get production data */
 281         if (read_eeprom(&header))
 282                 return 0;
 283
 284         /* setup MAC1 */
 285         mac_addr[0] = header.MAC1[0];
 286         mac_addr[1] = header.MAC1[1];
 287         mac_addr[2] = header.MAC1[2];
 288         mac_addr[3] = header.MAC1[3];
 289         mac_addr[4] = header.MAC1[4];
 290         mac_addr[5] = header.MAC1[5];
 291
 292
 293         node = fdt_path_offset(blob, "ethernet0");
 294         if (node < 0) {
 295                 printf("no ethernet0 path offset\n");
 296                 return -ENODEV;
 297         }
 298
 299         ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
 300         if (ret) {
 301                 printf("error setting mac-address property\n");
 302                 return -ENODEV;
 303         }
 304
 305         /* setup MAC2 */
 306         mac_addr[0] = header.MAC2[0];
 307         mac_addr[1] = header.MAC2[1];
 308         mac_addr[2] = header.MAC2[2];
 309         mac_addr[3] = header.MAC2[3];
 310         mac_addr[4] = header.MAC2[4];
 311         mac_addr[5] = header.MAC2[5];
 312
 313         node = fdt_path_offset(blob, "ethernet1");
 314         if (node < 0) {
 315                 printf("no ethernet1 path offset\n");
 316                 return -ENODEV;
 317         }
 318
 319         ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
 320         if (ret) {
 321                 printf("error setting mac-address property\n");
 322                 return -ENODEV;
 323         }
 324
 325         printf("\nFDT was successfully setup\n");
 326
 327         return 0;
 328 }
 329
 330 static struct module_pin_mux pcie_sw_pin_mux[] = {
 331         {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )},     /* GPIO3_4 */
 332         {-1},
 333 };
 334
 335 static struct module_pin_mux dip_pin_mux[] = {
 336         {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )},     /* GPIO1_12 */
 337         {OFFSET(gpmc_ad13), (MODE(7)  | RXACTIVE )},    /* GPIO1_13 */
 338         {OFFSET(gpmc_ad14), (MODE(7)  | RXACTIVE )},    /* GPIO1_14 */
 339         {OFFSET(gpmc_ad15), (MODE(7)  | RXACTIVE )},    /* GPIO1_15 */
 340         {-1},
 341 };
 342
 343 #ifdef CONFIG_BOARD_LATE_INIT
 344 int board_late_init(void)
 345 {
 346 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 347         BSP_VS_HWPARAM header;
 348         char model[4];
 349
 350         /* get production data */
 351         if (read_eeprom(&header)) {
 352                 strcpy(model, "211");
 353         } else {
 354                 sprintf(model, "%d", header.SystemId);
 355                 if (header.SystemId == 215) {
 356                         configure_module_pin_mux(dip_pin_mux);
 357                         baltos_set_console();
 358                 }
 359         }
 360
 361         /* turn power for the mPCIe slot */
 362         configure_module_pin_mux(pcie_sw_pin_mux);
 363         if (gpio_request(MPCIE_SW, "mpcie_sw")) {
 364                 printf("failed to export GPIO %d\n", MPCIE_SW);
 365                 return -ENODEV;
 366         }
 367         if (gpio_direction_output(MPCIE_SW, 1)) {
 368                 printf("failed to set GPIO %d direction\n", MPCIE_SW);
 369                 return -ENODEV;
 370         }
 371
 372         env_set("board_name", model);
 373 #endif
 374
 375         return 0;
 376 }
 377 #endif
 378
 379 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 380         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 381 static void cpsw_control(int enabled)
 382 {
 383         /* VTP can be added here */
 384
 385         return;
 386 }
 387
 388 static struct cpsw_slave_data cpsw_slaves[] = {
 389         {
 390                 .slave_reg_ofs  = 0x208,
 391                 .sliver_reg_ofs = 0xd80,
 392                 .phy_addr       = 0,
 393         },
 394         {
 395                 .slave_reg_ofs  = 0x308,
 396                 .sliver_reg_ofs = 0xdc0,
 397                 .phy_addr       = 7,
 398         },
 399 };
 400
 401 static struct cpsw_platform_data cpsw_data = {
 402         .mdio_base              = CPSW_MDIO_BASE,
 403         .cpsw_base              = CPSW_BASE,
 404         .mdio_div               = 0xff,
 405         .channels               = 8,
 406         .cpdma_reg_ofs          = 0x800,
 407         .slaves                 = 2,
 408         .slave_data             = cpsw_slaves,
 409         .active_slave           = 1,
 410         .ale_reg_ofs            = 0xd00,
 411         .ale_entries            = 1024,
 412         .host_port_reg_ofs      = 0x108,
 413         .hw_stats_reg_ofs       = 0x900,
 414         .bd_ram_ofs             = 0x2000,
 415         .mac_control            = (1 << 5),
 416         .control                = cpsw_control,
 417         .host_port_num          = 0,
 418         .version                = CPSW_CTRL_VERSION_2,
 419 };
 420 #endif
 421
 422 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
 423                 && defined(CONFIG_SPL_BUILD)) || \
 424         ((defined(CONFIG_DRIVER_TI_CPSW) || \
 425           defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
 426          !defined(CONFIG_SPL_BUILD))
 427 int board_eth_init(bd_t *bis)
 428 {
 429         int rv, n = 0;
 430         uint8_t mac_addr[6];
 431         uint32_t mac_hi, mac_lo;
 432
 433         /*
 434          * Note here that we're using CPSW1 since that has a 1Gbit PHY while
 435          * CSPW0 has a 100Mbit PHY.
 436          *
 437          * On product, CPSW1 maps to port labeled WAN.
 438          */
 439
 440         /* try reading mac address from efuse */
 441         mac_lo = readl(&cdev->macid1l);
 442         mac_hi = readl(&cdev->macid1h);
 443         mac_addr[0] = mac_hi & 0xFF;
 444         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 445         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 446         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 447         mac_addr[4] = mac_lo & 0xFF;
 448         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 449
 450 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 451         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 452         if (!env_get("ethaddr")) {
 453                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 454
 455                 if (is_valid_ethaddr(mac_addr))
 456                         eth_env_set_enetaddr("ethaddr", mac_addr);
 457         }
 458
 459 #ifdef CONFIG_DRIVER_TI_CPSW
 460         writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
 461         cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
 462         rv = cpsw_register(&cpsw_data);
 463         if (rv < 0)
 464                 printf("Error %d registering CPSW switch\n", rv);
 465         else
 466                 n += rv;
 467 #endif
 468
 469         /*
 470          *
 471          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 472          * operating points.  So we must set the TX clock delay feature
 473          * in the AR8051 PHY.  Since we only support a single ethernet
 474          * device in U-Boot, we only do this for the first instance.
 475          */
 476 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 477 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 478 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 479 #define AR8051_RGMII_TX_CLK_DLY         0x100
 480         const char *devname;
 481         devname = miiphy_get_current_dev();
 482
 483         miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
 484                         AR8051_DEBUG_RGMII_CLK_DLY_REG);
 485         miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
 486                         AR8051_RGMII_TX_CLK_DLY);
 487 #endif
 488         return n;
 489 }
 490 #endif