4 * Board functions for TI AM335X based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h>
23 #include <asm/arch/mux.h>
30 #include <power/tps65217.h>
31 #include <power/tps65910.h>
32 #include <environment.h>
36 DECLARE_GLOBAL_DATA_PTR
;
38 /* GPIO that controls power to DDR on EVM-SK */
39 #define GPIO_DDR_VTT_EN 7
42 static struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
44 static int baltos_set_console(void)
49 for (i
= 0; i
< 4; i
++) {
50 sprintf(buf
, "dip_s%d", i
+ 1);
52 if (gpio_request(DIP_S1
+ i
, buf
)) {
53 printf("failed to export GPIO %d\n", DIP_S1
+ i
);
57 if (gpio_direction_input(DIP_S1
+ i
)) {
58 printf("failed to set GPIO %d direction\n", DIP_S1
+ i
);
62 val
= gpio_get_value(DIP_S1
+ i
);
66 printf("DIPs: 0x%1x\n", (~dips
) & 0xf);
68 if ((dips
& 0xf) == 0xe)
69 setenv("console", "ttyUSB0,115200n8");
74 static int read_eeprom(BSP_VS_HWPARAM
*header
)
78 /* Check if baseboard eeprom is available */
79 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR
)) {
80 puts("Could not probe the EEPROM; something fundamentally "
81 "wrong on the I2C bus.\n");
85 /* read the eeprom using i2c */
86 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR
, 0, 1, (uchar
*)header
,
87 sizeof(BSP_VS_HWPARAM
))) {
88 puts("Could not read the EEPROM; something fundamentally"
89 " wrong on the I2C bus.\n");
93 if (header
->Magic
!= 0xDEADBEEF) {
95 printf("Incorrect magic number (0x%x) in EEPROM\n",
98 /* fill default values */
99 header
->SystemId
= 211;
100 header
->MAC1
[0] = 0x00;
101 header
->MAC1
[1] = 0x00;
102 header
->MAC1
[2] = 0x00;
103 header
->MAC1
[3] = 0x00;
104 header
->MAC1
[4] = 0x00;
105 header
->MAC1
[5] = 0x01;
107 header
->MAC2
[0] = 0x00;
108 header
->MAC2
[1] = 0x00;
109 header
->MAC2
[2] = 0x00;
110 header
->MAC2
[3] = 0x00;
111 header
->MAC2
[4] = 0x00;
112 header
->MAC2
[5] = 0x02;
114 header
->MAC3
[0] = 0x00;
115 header
->MAC3
[1] = 0x00;
116 header
->MAC3
[2] = 0x00;
117 header
->MAC3
[3] = 0x00;
118 header
->MAC3
[4] = 0x00;
119 header
->MAC3
[5] = 0x03;
125 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
127 static const struct ddr_data ddr3_baltos_data
= {
128 .datardsratio0
= MT41K256M16HA125E_RD_DQS
,
129 .datawdsratio0
= MT41K256M16HA125E_WR_DQS
,
130 .datafwsratio0
= MT41K256M16HA125E_PHY_FIFO_WE
,
131 .datawrsratio0
= MT41K256M16HA125E_PHY_WR_DATA
,
134 static const struct cmd_control ddr3_baltos_cmd_ctrl_data
= {
135 .cmd0csratio
= MT41K256M16HA125E_RATIO
,
136 .cmd0iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
138 .cmd1csratio
= MT41K256M16HA125E_RATIO
,
139 .cmd1iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
141 .cmd2csratio
= MT41K256M16HA125E_RATIO
,
142 .cmd2iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
145 static struct emif_regs ddr3_baltos_emif_reg_data
= {
146 .sdram_config
= MT41K256M16HA125E_EMIF_SDCFG
,
147 .ref_ctrl
= MT41K256M16HA125E_EMIF_SDREF
,
148 .sdram_tim1
= MT41K256M16HA125E_EMIF_TIM1
,
149 .sdram_tim2
= MT41K256M16HA125E_EMIF_TIM2
,
150 .sdram_tim3
= MT41K256M16HA125E_EMIF_TIM3
,
151 .zq_config
= MT41K256M16HA125E_ZQ_CFG
,
152 .emif_ddr_phy_ctlr_1
= MT41K256M16HA125E_EMIF_READ_LATENCY
,
155 #ifdef CONFIG_SPL_OS_BOOT
156 int spl_start_uboot(void)
158 /* break into full u-boot on 'c' */
159 return (serial_tstc() && serial_getc() == 'c');
163 #define OSC (V_OSCK/1000000)
164 const struct dpll_params dpll_ddr
= {
165 266, OSC
-1, 1, -1, -1, -1, -1};
166 const struct dpll_params dpll_ddr_evm_sk
= {
167 303, OSC
-1, 1, -1, -1, -1, -1};
168 const struct dpll_params dpll_ddr_baltos
= {
169 400, OSC
-1, 1, -1, -1, -1, -1};
171 void am33xx_spl_board_init(void)
176 /* Get the frequency */
177 dpll_mpu_opp100
.m
= am335x_get_efuse_mpu_max_freq(cdev
);
180 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
181 * MPU frequencies we support we use a CORE voltage of
182 * 1.1375V. For MPU voltage we need to switch based on
183 * the frequency we are running at.
187 printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED
);
189 if (i2c_probe(TPS65910_CTRL_I2C_ADDR
)) {
190 puts("i2c: cannot access TPS65910\n");
195 * Depending on MPU clock and PG we will need a different
196 * VDD to drive at that speed.
198 sil_rev
= readl(&cdev
->deviceid
) >> 28;
199 mpu_vdd
= am335x_get_tps65910_mpu_vdd(sil_rev
,
202 /* Tell the TPS65910 to use i2c */
203 tps65910_set_i2c_control();
205 /* First update MPU voltage. */
206 if (tps65910_voltage_update(MPU
, mpu_vdd
))
209 /* Second, update the CORE voltage. */
210 if (tps65910_voltage_update(CORE
, TPS65910_OP_REG_SEL_1_1_3
))
213 /* Set CORE Frequencies to OPP100 */
214 do_setup_dpll(&dpll_core_regs
, &dpll_core_opp100
);
216 /* Set MPU Frequency to what we detected now that voltages are set */
217 do_setup_dpll(&dpll_mpu_regs
, &dpll_mpu_opp100
);
219 writel(0x000010ff, PRM_DEVICE_INST
+ 4);
222 const struct dpll_params
*get_dpll_ddr_params(void)
224 enable_i2c1_pin_mux();
227 return &dpll_ddr_baltos
;
230 void set_uart_mux_conf(void)
232 enable_uart0_pin_mux();
235 void set_mux_conf_regs(void)
237 enable_board_pin_mux();
240 const struct ctrl_ioregs ioregs_baltos
= {
241 .cm0ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
242 .cm1ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
243 .cm2ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
244 .dt0ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
245 .dt1ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
248 void sdram_init(void)
250 gpio_request(GPIO_DDR_VTT_EN
, "ddr_vtt_en");
251 gpio_direction_output(GPIO_DDR_VTT_EN
, 1);
253 config_ddr(400, &ioregs_baltos
,
255 &ddr3_baltos_cmd_ctrl_data
,
256 &ddr3_baltos_emif_reg_data
, 0);
261 * Basic board specific setup. Pinmux has been handled already.
265 #if defined(CONFIG_HW_WATCHDOG)
269 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
270 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
276 int ft_board_setup(void *blob
, bd_t
*bd
)
279 unsigned char mac_addr
[6];
280 BSP_VS_HWPARAM header
;
282 /* get production data */
283 if (read_eeprom(&header
))
287 mac_addr
[0] = header
.MAC1
[0];
288 mac_addr
[1] = header
.MAC1
[1];
289 mac_addr
[2] = header
.MAC1
[2];
290 mac_addr
[3] = header
.MAC1
[3];
291 mac_addr
[4] = header
.MAC1
[4];
292 mac_addr
[5] = header
.MAC1
[5];
295 node
= fdt_path_offset(blob
, "/ocp/ethernet/slave@4a100200");
297 printf("no /soc/fman/ethernet path offset\n");
301 ret
= fdt_setprop(blob
, node
, "mac-address", &mac_addr
, 6);
303 printf("error setting local-mac-address property\n");
308 mac_addr
[0] = header
.MAC2
[0];
309 mac_addr
[1] = header
.MAC2
[1];
310 mac_addr
[2] = header
.MAC2
[2];
311 mac_addr
[3] = header
.MAC2
[3];
312 mac_addr
[4] = header
.MAC2
[4];
313 mac_addr
[5] = header
.MAC2
[5];
315 node
= fdt_path_offset(blob
, "/ocp/ethernet/slave@4a100300");
317 printf("no /soc/fman/ethernet path offset\n");
321 ret
= fdt_setprop(blob
, node
, "mac-address", &mac_addr
, 6);
323 printf("error setting local-mac-address property\n");
327 printf("\nFDT was successfully setup\n");
332 static struct module_pin_mux dip_pin_mux
[] = {
333 {OFFSET(gpmc_ad12
), (MODE(7) | RXACTIVE
)}, /* GPIO1_12 */
334 {OFFSET(gpmc_ad13
), (MODE(7) | RXACTIVE
)}, /* GPIO1_13 */
335 {OFFSET(gpmc_ad14
), (MODE(7) | RXACTIVE
)}, /* GPIO1_14 */
336 {OFFSET(gpmc_ad15
), (MODE(7) | RXACTIVE
)}, /* GPIO1_15 */
340 #ifdef CONFIG_BOARD_LATE_INIT
341 int board_late_init(void)
343 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
344 BSP_VS_HWPARAM header
;
347 /* get production data */
348 if (read_eeprom(&header
)) {
349 sprintf(model
, "211");
351 sprintf(model
, "%d", header
.SystemId
);
352 if (header
.SystemId
== 215) {
353 configure_module_pin_mux(dip_pin_mux
);
354 baltos_set_console();
357 setenv("board_name", model
);
364 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
365 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
366 static void cpsw_control(int enabled
)
368 /* VTP can be added here */
373 static struct cpsw_slave_data cpsw_slaves
[] = {
375 .slave_reg_ofs
= 0x208,
376 .sliver_reg_ofs
= 0xd80,
380 .slave_reg_ofs
= 0x308,
381 .sliver_reg_ofs
= 0xdc0,
386 static struct cpsw_platform_data cpsw_data
= {
387 .mdio_base
= CPSW_MDIO_BASE
,
388 .cpsw_base
= CPSW_BASE
,
391 .cpdma_reg_ofs
= 0x800,
393 .slave_data
= cpsw_slaves
,
395 .ale_reg_ofs
= 0xd00,
397 .host_port_reg_ofs
= 0x108,
398 .hw_stats_reg_ofs
= 0x900,
399 .bd_ram_ofs
= 0x2000,
400 .mac_control
= (1 << 5),
401 .control
= cpsw_control
,
403 .version
= CPSW_CTRL_VERSION_2
,
407 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
408 && defined(CONFIG_SPL_BUILD)) || \
409 ((defined(CONFIG_DRIVER_TI_CPSW) || \
410 defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
411 !defined(CONFIG_SPL_BUILD))
412 int board_eth_init(bd_t
*bis
)
416 uint32_t mac_hi
, mac_lo
;
417 __maybe_unused
struct am335x_baseboard_id header
;
420 * Note here that we're using CPSW1 since that has a 1Gbit PHY while
421 * CSPW0 has a 100Mbit PHY.
423 * On product, CPSW1 maps to port labeled WAN.
426 /* try reading mac address from efuse */
427 mac_lo
= readl(&cdev
->macid1l
);
428 mac_hi
= readl(&cdev
->macid1h
);
429 mac_addr
[0] = mac_hi
& 0xFF;
430 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
431 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
432 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
433 mac_addr
[4] = mac_lo
& 0xFF;
434 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
436 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
437 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
438 if (!getenv("ethaddr")) {
439 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
441 if (is_valid_ethaddr(mac_addr
))
442 eth_setenv_enetaddr("ethaddr", mac_addr
);
445 #ifdef CONFIG_DRIVER_TI_CPSW
446 writel((GMII1_SEL_RMII
| GMII2_SEL_RGMII
| RGMII2_IDMODE
), &cdev
->miisel
);
447 cpsw_slaves
[1].phy_if
= PHY_INTERFACE_MODE_RGMII
;
448 rv
= cpsw_register(&cpsw_data
);
450 printf("Error %d registering CPSW switch\n", rv
);
457 * CPSW RGMII Internal Delay Mode is not supported in all PVT
458 * operating points. So we must set the TX clock delay feature
459 * in the AR8051 PHY. Since we only support a single ethernet
460 * device in U-Boot, we only do this for the first instance.
462 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
463 #define AR8051_PHY_DEBUG_DATA_REG 0x1e
464 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
465 #define AR8051_RGMII_TX_CLK_DLY 0x100
467 devname
= miiphy_get_current_dev();
469 miiphy_write(devname
, 0x7, AR8051_PHY_DEBUG_ADDR_REG
,
470 AR8051_DEBUG_RGMII_CLK_DLY_REG
);
471 miiphy_write(devname
, 0x7, AR8051_PHY_DEBUG_DATA_REG
,
472 AR8051_RGMII_TX_CLK_DLY
);