board/w7o/init.S

   1 /******************************************************************************
   2  *   This source code is dual-licensed.  You may use it under the terms of the
   3  *   GNU General Public License version 2, or under the license below.
   4  *
   5  *       This source code has been made available to you by IBM on an AS-IS
   6  *       basis.  Anyone receiving this source is licensed under IBM
   7  *       copyrights to use it in any way he or she deems fit, including
   8  *       copying it, modifying it, compiling it, and redistributing it either
   9  *       with or without modifications.  No license under IBM patents or
  10  *       patent applications is to be implied by the copyright license.
  11  *
  12  *       Any user of this software should understand that IBM cannot provide
  13  *       technical support for this software and will not be responsible for
  14  *       any consequences resulting from the use of this software.
  15  *
  16  *       Any person who transfers this source code or any derivative work
  17  *       must include the IBM copyright notice, this paragraph, and the
  18  *       preceding two paragraphs in the transferred software.
  19  *
  20  *       COPYRIGHT   I B M   CORPORATION 1995
  21  *       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  22  *
  23  *****************************************************************************/
  24 #include <config.h>
  25 #include <asm/ppc4xx.h>
  26
  27 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  28
  29 #include <ppc_asm.tmpl>
  30 #include <ppc_defs.h>
  31
  32 #include <asm/cache.h>
  33 #include <asm/mmu.h>
  34
  35 /******************************************************************************
  36  * Function:    ext_bus_cntlr_init
  37  *
  38  * Description: Configures EBC Controller and a few basic chip selects.
  39  *
  40  *              CS0 is setup to get the Boot Flash out of the addresss range
  41  *              so that we may setup a stack.  CS7 is setup so that we can
  42  *              access and reset the hardware watchdog.
  43  *
  44  *              IMPORTANT: For pass1 this code must run from
  45  *              cache since you can not reliably change a peripheral banks
  46  *              timing register (pbxap) while running code from that bank.
  47  *              For ex., since we are running from ROM on bank 0, we can NOT
  48  *              execute the code that modifies bank 0 timings from ROM, so
  49  *              we run it from cache.
  50  *
  51  * Notes:       Does NOT use the stack.
  52  *****************************************************************************/
  53         .section ".text"
  54         .align  2
  55         .globl  ext_bus_cntlr_init
  56         .type   ext_bus_cntlr_init, @function
  57 ext_bus_cntlr_init:
  58         mflr    r0
  59         /********************************************************************
  60          * Prefetch entire ext_bus_cntrl_init function into the icache.
  61          * This is necessary because we are going to change the same CS we
  62          * are executing from.  Otherwise a CPU lockup may occur.
  63          *******************************************************************/
  64         bl      ..getAddr
  65 ..getAddr:
  66         mflr    r3                      /* get address of ..getAddr */
  67
  68         /* Calculate number of cache lines for this function */
  69         addi    r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
  70         mtctr   r4
  71 ..ebcloop:
  72         icbt    r0, r3                  /* prefetch cache line for addr in r3*/
  73         addi    r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
  74         bdnz    ..ebcloop               /* continue for $CTR cache lines */
  75
  76         /********************************************************************
  77          * Delay to ensure all accesses to ROM are complete before changing
  78          * bank 0 timings. 200usec should be enough.
  79          * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
  80          *******************************************************************/
  81         addis   r3, 0, 0x0
  82         ori     r3, r3, 0xA000          /* wait 200us from reset */
  83         mtctr   r3
  84 ..spinlp:
  85         bdnz    ..spinlp                /* spin loop */
  86
  87         /********************************************************************
  88          * Setup External Bus Controller (EBC).
  89          *******************************************************************/
  90         addi    r3, 0, EBC0_CFG
  91         mtdcr   EBC0_CFGADDR, r3
  92         addis   r4, 0, 0xb040           /* Device base timeout = 1024 cycles */
  93         ori     r4, r4, 0x0             /* Drive CS with external master */
  94         mtdcr   EBC0_CFGDATA, r4
  95
  96         /********************************************************************
  97          * Change PCIINT signal to PerWE
  98          *******************************************************************/
  99         mfdcr   r4, CPC0_CR1
 100         ori     r4, r4, 0x4000
 101         mtdcr   CPC0_CR1, r4
 102
 103         /********************************************************************
 104          * Memory Bank 0 (Flash Bank 0) initialization
 105          *******************************************************************/
 106         addi    r3, 0, PB1AP
 107         mtdcr   EBC0_CFGADDR, r3
 108         addis   r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h
 109         ori     r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l
 110         mtdcr   EBC0_CFGDATA, r4
 111
 112         addi    r3, 0, PB0CR
 113         mtdcr   EBC0_CFGADDR, r3
 114         addis   r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h
 115         ori     r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l
 116         mtdcr   EBC0_CFGDATA, r4
 117
 118         /********************************************************************
 119          * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
 120          *******************************************************************/
 121         addi    r3, 0, PB7AP
 122         mtdcr   EBC0_CFGADDR, r3
 123         addis   r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h
 124         ori     r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l
 125         mtdcr   EBC0_CFGDATA, r4
 126
 127         addi    r3, 0, PB7CR
 128         mtdcr   EBC0_CFGADDR, r3
 129         addis   r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h
 130         ori     r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l
 131         mtdcr   EBC0_CFGDATA, r4
 132
 133         /* We are all done */
 134         mtlr    r0                      /* Restore link register */
 135         blr                             /* Return to calling function */
 136 .Lfe0:  .size   ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
 137 /* end ext_bus_cntlr_init() */
 138
 139 /******************************************************************************
 140  * Function:    sdram_init
 141  *
 142  * Description: Configures SDRAM memory banks.
 143  *
 144  *              Serial Presence Detect, "SPD," reads the SDRAM EEPROM
 145  *              via the IIC bus and then configures the SDRAM memory
 146  *              banks appropriately. If Auto Memory Configuration is
 147  *              is not used, it is assumed that a 4MB 11x8x2, non-ECC,
 148  *              SDRAM is soldered down.
 149  *
 150  * Notes:       Expects that the stack is already setup.
 151  *****************************************************************************/
 152         .section ".text"
 153         .align  2
 154         .globl  sdram_init
 155         .type   sdram_init, @function
 156 sdram_init:
 157         /* save the return info on stack */
 158         mflr    r0                      /* Get link register */
 159         stwu    r1, -8(r1)              /* Save back chain and move SP */
 160         stw     r0, +12(r1)             /* Save link register */
 161
 162         /*
 163          * First call spd_sdram to try to init SDRAM according to the
 164          * contents of the SPD EEPROM.  If the SPD EEPROM is blank or
 165          * erronious, spd_sdram returns 0 in R3.
 166          */
 167         li      r3,0
 168         bl      spd_sdram
 169         addic.  r3, r3, 0               /* Check for error, save dram size */
 170         bne     ..sdri_done             /* If it worked, we're done... */
 171
 172         /********************************************************************
 173          * If SPD detection fails, we'll default to 4MB, 11x8x2, as this
 174          * is the SMALLEST SDRAM size the 405 supports.  We can do this
 175          * because W7O boards have soldered on RAM, and there will always
 176          * be some amount present.  If we were using DIMMs, we should hang
 177          * the board instead, since it doesn't have any RAM to continue
 178          * running with.
 179          *******************************************************************/
 180
 181         /*
 182          * Disable memory controller to allow
 183          * values to be changed.
 184          */
 185         addi    r3, 0, SDRAM0_CFG
 186         mtdcr   SDRAM0_CFGADDR, r3
 187         addis   r4, 0, 0x0
 188         ori     r4, r4, 0x0
 189         mtdcr   SDRAM0_CFGDATA, r4
 190
 191         /*
 192          * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
 193          * All other banks are disabled.
 194          */
 195         addi    r3, 0, SDRAM0_B0CR
 196         mtdcr   SDRAM0_CFGADDR, r3
 197         addis   r4, 0, 0x0000           /* BA=0x0, SZ=4MB */
 198         ori     r4, r4, 0x8001          /* Mode is 5, 11x8x2or4, BE=Enabled */
 199         mtdcr   SDRAM0_CFGDATA, r4
 200
 201         /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
 202         addi    r4, 0, 0                /* Zero the data reg */
 203
 204         addi    r3, r3, 4               /* Point to MB1CF reg */
 205         mtdcr   SDRAM0_CFGADDR, r3              /* Set the address */
 206         mtdcr   SDRAM0_CFGDATA, r4              /* Zero the reg */
 207
 208         addi    r3, r3, 4               /* Point to MB2CF reg */
 209         mtdcr   SDRAM0_CFGADDR, r3              /* Set the address */
 210         mtdcr   SDRAM0_CFGDATA, r4              /* Zero the reg */
 211
 212         addi    r3, r3, 4               /* Point to MB3CF reg */
 213         mtdcr   SDRAM0_CFGADDR, r3              /* Set the address */
 214         mtdcr   SDRAM0_CFGDATA, r4              /* Zero the reg */
 215
 216         /********************************************************************
 217          * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
 218          * To set the appropriate timings, we assume sdram is
 219          * 100MHz (pc100 compliant).
 220          *******************************************************************/
 221
 222         /*
 223          * Set up SDTR1
 224          */
 225         addi    r3, 0, SDRAM0_TR
 226         mtdcr   SDRAM0_CFGADDR, r3
 227         addis   r4, 0, 0x0086           /* SDTR1 value for 100Mhz */
 228         ori     r4, r4, 0x400D
 229         mtdcr   SDRAM0_CFGDATA, r4
 230
 231         /*
 232          * Set RTR
 233          */
 234         addi    r3, 0, SDRAM0_RTR
 235         mtdcr   SDRAM0_CFGADDR, r3
 236         addis   r4, 0, 0x05F0           /* RTR refresh val = 15.625ms@100Mhz */
 237         mtdcr   SDRAM0_CFGDATA, r4
 238
 239         /********************************************************************
 240          * Delay to ensure 200usec have elapsed since reset. Assume worst
 241          * case that the core is running 200Mhz:
 242          *        200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
 243          *******************************************************************/
 244         addis   r3, 0, 0x0000
 245         ori     r3, r3, 0xA000          /* Wait 200us from reset */
 246         mtctr   r3
 247 ..spinlp2:
 248         bdnz    ..spinlp2               /* spin loop */
 249
 250         /********************************************************************
 251          * Set memory controller options reg, MCOPT1.
 252          *******************************************************************/
 253         addi    r3, 0, SDRAM0_CFG
 254         mtdcr   SDRAM0_CFGADDR, r3
 255         addis   r4, 0, 0x80E0           /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
 256         ori     r4, r4, 0x0000          /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
 257         mtdcr   SDRAM0_CFGDATA, r4              /* EMDULR=1 */
 258
 259 ..sdri_done:
 260         /* restore and return */
 261         lwz     r0, +12(r1)             /* Get saved link register */
 262         addi    r1, r1, +8              /* Remove frame from stack */
 263         mtlr    r0                      /* Restore link register */
 264         blr                             /* Return to calling function */
 265 .Lfe1:  .size   sdram_init,.Lfe1-sdram_init
 266 /* end sdram_init() */