board/w7o/init.S

   1 /*
   2  * SPDX-License-Identifier:     GPL-2.0 IBM-pibs
   3  */
   4 #include <config.h>
   5 #include <asm/ppc4xx.h>
   6
   7 #include <ppc_asm.tmpl>
   8 #include <ppc_defs.h>
   9
  10 #include <asm/cache.h>
  11 #include <asm/mmu.h>
  12
  13 /******************************************************************************
  14  * Function:    ext_bus_cntlr_init
  15  *
  16  * Description: Configures EBC Controller and a few basic chip selects.
  17  *
  18  *              CS0 is setup to get the Boot Flash out of the addresss range
  19  *              so that we may setup a stack.  CS7 is setup so that we can
  20  *              access and reset the hardware watchdog.
  21  *
  22  *              IMPORTANT: For pass1 this code must run from
  23  *              cache since you can not reliably change a peripheral banks
  24  *              timing register (pbxap) while running code from that bank.
  25  *              For ex., since we are running from ROM on bank 0, we can NOT
  26  *              execute the code that modifies bank 0 timings from ROM, so
  27  *              we run it from cache.
  28  *
  29  * Notes:       Does NOT use the stack.
  30  *****************************************************************************/
  31         .section ".text"
  32         .align  2
  33         .globl  ext_bus_cntlr_init
  34         .type   ext_bus_cntlr_init, @function
  35 ext_bus_cntlr_init:
  36         mflr    r0
  37         /********************************************************************
  38          * Prefetch entire ext_bus_cntrl_init function into the icache.
  39          * This is necessary because we are going to change the same CS we
  40          * are executing from.  Otherwise a CPU lockup may occur.
  41          *******************************************************************/
  42         bl      ..getAddr
  43 ..getAddr:
  44         mflr    r3                      /* get address of ..getAddr */
  45
  46         /* Calculate number of cache lines for this function */
  47         addi    r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
  48         mtctr   r4
  49 ..ebcloop:
  50         icbt    r0, r3                  /* prefetch cache line for addr in r3*/
  51         addi    r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
  52         bdnz    ..ebcloop               /* continue for $CTR cache lines */
  53
  54         /********************************************************************
  55          * Delay to ensure all accesses to ROM are complete before changing
  56          * bank 0 timings. 200usec should be enough.
  57          * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
  58          *******************************************************************/
  59         addis   r3, 0, 0x0
  60         ori     r3, r3, 0xA000          /* wait 200us from reset */
  61         mtctr   r3
  62 ..spinlp:
  63         bdnz    ..spinlp                /* spin loop */
  64
  65         /********************************************************************
  66          * Setup External Bus Controller (EBC).
  67          *******************************************************************/
  68         addi    r3, 0, EBC0_CFG
  69         mtdcr   EBC0_CFGADDR, r3
  70         addis   r4, 0, 0xb040           /* Device base timeout = 1024 cycles */
  71         ori     r4, r4, 0x0             /* Drive CS with external master */
  72         mtdcr   EBC0_CFGDATA, r4
  73
  74         /********************************************************************
  75          * Change PCIINT signal to PerWE
  76          *******************************************************************/
  77         mfdcr   r4, CPC0_CR1
  78         ori     r4, r4, 0x4000
  79         mtdcr   CPC0_CR1, r4
  80
  81         /********************************************************************
  82          * Memory Bank 0 (Flash Bank 0) initialization
  83          *******************************************************************/
  84         addi    r3, 0, PB1AP
  85         mtdcr   EBC0_CFGADDR, r3
  86         addis   r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h
  87         ori     r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l
  88         mtdcr   EBC0_CFGDATA, r4
  89
  90         addi    r3, 0, PB0CR
  91         mtdcr   EBC0_CFGADDR, r3
  92         addis   r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h
  93         ori     r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l
  94         mtdcr   EBC0_CFGDATA, r4
  95
  96         /********************************************************************
  97          * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
  98          *******************************************************************/
  99         addi    r3, 0, PB7AP
 100         mtdcr   EBC0_CFGADDR, r3
 101         addis   r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h
 102         ori     r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l
 103         mtdcr   EBC0_CFGDATA, r4
 104
 105         addi    r3, 0, PB7CR
 106         mtdcr   EBC0_CFGADDR, r3
 107         addis   r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h
 108         ori     r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l
 109         mtdcr   EBC0_CFGDATA, r4
 110
 111         /* We are all done */
 112         mtlr    r0                      /* Restore link register */
 113         blr                             /* Return to calling function */
 114 .Lfe0:  .size   ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
 115 /* end ext_bus_cntlr_init() */
 116
 117 /******************************************************************************
 118  * Function:    sdram_init
 119  *
 120  * Description: Configures SDRAM memory banks.
 121  *
 122  *              Serial Presence Detect, "SPD," reads the SDRAM EEPROM
 123  *              via the IIC bus and then configures the SDRAM memory
 124  *              banks appropriately. If Auto Memory Configuration is
 125  *              is not used, it is assumed that a 4MB 11x8x2, non-ECC,
 126  *              SDRAM is soldered down.
 127  *
 128  * Notes:       Expects that the stack is already setup.
 129  *****************************************************************************/
 130         .section ".text"
 131         .align  2
 132         .globl  sdram_init
 133         .type   sdram_init, @function
 134 sdram_init:
 135         /* save the return info on stack */
 136         mflr    r0                      /* Get link register */
 137         stwu    r1, -8(r1)              /* Save back chain and move SP */
 138         stw     r0, +12(r1)             /* Save link register */
 139
 140         /*
 141          * First call spd_sdram to try to init SDRAM according to the
 142          * contents of the SPD EEPROM.  If the SPD EEPROM is blank or
 143          * erronious, spd_sdram returns 0 in R3.
 144          */
 145         li      r3,0
 146         bl      spd_sdram
 147         addic.  r3, r3, 0               /* Check for error, save dram size */
 148         bne     ..sdri_done             /* If it worked, we're done... */
 149
 150         /********************************************************************
 151          * If SPD detection fails, we'll default to 4MB, 11x8x2, as this
 152          * is the SMALLEST SDRAM size the 405 supports.  We can do this
 153          * because W7O boards have soldered on RAM, and there will always
 154          * be some amount present.  If we were using DIMMs, we should hang
 155          * the board instead, since it doesn't have any RAM to continue
 156          * running with.
 157          *******************************************************************/
 158
 159         /*
 160          * Disable memory controller to allow
 161          * values to be changed.
 162          */
 163         addi    r3, 0, SDRAM0_CFG
 164         mtdcr   SDRAM0_CFGADDR, r3
 165         addis   r4, 0, 0x0
 166         ori     r4, r4, 0x0
 167         mtdcr   SDRAM0_CFGDATA, r4
 168
 169         /*
 170          * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
 171          * All other banks are disabled.
 172          */
 173         addi    r3, 0, SDRAM0_B0CR
 174         mtdcr   SDRAM0_CFGADDR, r3
 175         addis   r4, 0, 0x0000           /* BA=0x0, SZ=4MB */
 176         ori     r4, r4, 0x8001          /* Mode is 5, 11x8x2or4, BE=Enabled */
 177         mtdcr   SDRAM0_CFGDATA, r4
 178
 179         /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
 180         addi    r4, 0, 0                /* Zero the data reg */
 181
 182         addi    r3, r3, 4               /* Point to MB1CF reg */
 183         mtdcr   SDRAM0_CFGADDR, r3              /* Set the address */
 184         mtdcr   SDRAM0_CFGDATA, r4              /* Zero the reg */
 185
 186         addi    r3, r3, 4               /* Point to MB2CF reg */
 187         mtdcr   SDRAM0_CFGADDR, r3              /* Set the address */
 188         mtdcr   SDRAM0_CFGDATA, r4              /* Zero the reg */
 189
 190         addi    r3, r3, 4               /* Point to MB3CF reg */
 191         mtdcr   SDRAM0_CFGADDR, r3              /* Set the address */
 192         mtdcr   SDRAM0_CFGDATA, r4              /* Zero the reg */
 193
 194         /********************************************************************
 195          * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
 196          * To set the appropriate timings, we assume sdram is
 197          * 100MHz (pc100 compliant).
 198          *******************************************************************/
 199
 200         /*
 201          * Set up SDTR1
 202          */
 203         addi    r3, 0, SDRAM0_TR
 204         mtdcr   SDRAM0_CFGADDR, r3
 205         addis   r4, 0, 0x0086           /* SDTR1 value for 100Mhz */
 206         ori     r4, r4, 0x400D
 207         mtdcr   SDRAM0_CFGDATA, r4
 208
 209         /*
 210          * Set RTR
 211          */
 212         addi    r3, 0, SDRAM0_RTR
 213         mtdcr   SDRAM0_CFGADDR, r3
 214         addis   r4, 0, 0x05F0           /* RTR refresh val = 15.625ms@100Mhz */
 215         mtdcr   SDRAM0_CFGDATA, r4
 216
 217         /********************************************************************
 218          * Delay to ensure 200usec have elapsed since reset. Assume worst
 219          * case that the core is running 200Mhz:
 220          *        200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
 221          *******************************************************************/
 222         addis   r3, 0, 0x0000
 223         ori     r3, r3, 0xA000          /* Wait 200us from reset */
 224         mtctr   r3
 225 ..spinlp2:
 226         bdnz    ..spinlp2               /* spin loop */
 227
 228         /********************************************************************
 229          * Set memory controller options reg, MCOPT1.
 230          *******************************************************************/
 231         addi    r3, 0, SDRAM0_CFG
 232         mtdcr   SDRAM0_CFGADDR, r3
 233         addis   r4, 0, 0x80E0           /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
 234         ori     r4, r4, 0x0000          /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
 235         mtdcr   SDRAM0_CFGDATA, r4              /* EMDULR=1 */
 236
 237 ..sdri_done:
 238         /* restore and return */
 239         lwz     r0, +12(r1)             /* Get saved link register */
 240         addi    r1, r1, +8              /* Remove frame from stack */
 241         mtlr    r0                      /* Restore link register */
 242         blr                             /* Return to calling function */
 243 .Lfe1:  .size   sdram_init,.Lfe1-sdram_init
 244 /* end sdram_init() */