1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Wandboard
4 * Author: Tungyi Lin <tungyilin1127@gmail.com>
5 * Richard Hu <hakahu@gmail.com>
8 #include <asm/arch/clock.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <linux/errno.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm/mach-imx/video.h>
17 #include <fsl_esdhc.h>
18 #include <asm/arch/crm_regs.h>
20 #include <asm/arch/sys_proto.h>
23 #if defined(CONFIG_SPL_BUILD)
24 #include <asm/arch/mx6-ddr.h>
31 #define IMX6DQ_DRIVE_STRENGTH 0x30
32 #define IMX6SDL_DRIVE_STRENGTH 0x28
33 #define IMX6QP_DRIVE_STRENGTH 0x28
35 /* configure MX6Q/DUAL mmdc DDR io registers */
36 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs
= {
37 .dram_sdclk_0
= IMX6DQ_DRIVE_STRENGTH
,
38 .dram_sdclk_1
= IMX6DQ_DRIVE_STRENGTH
,
39 .dram_cas
= IMX6DQ_DRIVE_STRENGTH
,
40 .dram_ras
= IMX6DQ_DRIVE_STRENGTH
,
41 .dram_reset
= IMX6DQ_DRIVE_STRENGTH
,
42 .dram_sdcke0
= IMX6DQ_DRIVE_STRENGTH
,
43 .dram_sdcke1
= IMX6DQ_DRIVE_STRENGTH
,
44 .dram_sdba2
= 0x00000000,
45 .dram_sdodt0
= IMX6DQ_DRIVE_STRENGTH
,
46 .dram_sdodt1
= IMX6DQ_DRIVE_STRENGTH
,
47 .dram_sdqs0
= IMX6DQ_DRIVE_STRENGTH
,
48 .dram_sdqs1
= IMX6DQ_DRIVE_STRENGTH
,
49 .dram_sdqs2
= IMX6DQ_DRIVE_STRENGTH
,
50 .dram_sdqs3
= IMX6DQ_DRIVE_STRENGTH
,
51 .dram_sdqs4
= IMX6DQ_DRIVE_STRENGTH
,
52 .dram_sdqs5
= IMX6DQ_DRIVE_STRENGTH
,
53 .dram_sdqs6
= IMX6DQ_DRIVE_STRENGTH
,
54 .dram_sdqs7
= IMX6DQ_DRIVE_STRENGTH
,
55 .dram_dqm0
= IMX6DQ_DRIVE_STRENGTH
,
56 .dram_dqm1
= IMX6DQ_DRIVE_STRENGTH
,
57 .dram_dqm2
= IMX6DQ_DRIVE_STRENGTH
,
58 .dram_dqm3
= IMX6DQ_DRIVE_STRENGTH
,
59 .dram_dqm4
= IMX6DQ_DRIVE_STRENGTH
,
60 .dram_dqm5
= IMX6DQ_DRIVE_STRENGTH
,
61 .dram_dqm6
= IMX6DQ_DRIVE_STRENGTH
,
62 .dram_dqm7
= IMX6DQ_DRIVE_STRENGTH
,
65 /* configure MX6QP mmdc DDR io registers */
66 static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs
= {
67 .dram_sdclk_0
= IMX6QP_DRIVE_STRENGTH
,
68 .dram_sdclk_1
= IMX6QP_DRIVE_STRENGTH
,
69 .dram_cas
= IMX6QP_DRIVE_STRENGTH
,
70 .dram_ras
= IMX6QP_DRIVE_STRENGTH
,
71 .dram_reset
= IMX6QP_DRIVE_STRENGTH
,
72 .dram_sdcke0
= IMX6QP_DRIVE_STRENGTH
,
73 .dram_sdcke1
= IMX6QP_DRIVE_STRENGTH
,
74 .dram_sdba2
= 0x00000000,
75 .dram_sdodt0
= IMX6QP_DRIVE_STRENGTH
,
76 .dram_sdodt1
= IMX6QP_DRIVE_STRENGTH
,
77 .dram_sdqs0
= IMX6QP_DRIVE_STRENGTH
,
78 .dram_sdqs1
= IMX6QP_DRIVE_STRENGTH
,
79 .dram_sdqs2
= IMX6QP_DRIVE_STRENGTH
,
80 .dram_sdqs3
= IMX6QP_DRIVE_STRENGTH
,
81 .dram_sdqs4
= IMX6QP_DRIVE_STRENGTH
,
82 .dram_sdqs5
= IMX6QP_DRIVE_STRENGTH
,
83 .dram_sdqs6
= IMX6QP_DRIVE_STRENGTH
,
84 .dram_sdqs7
= IMX6QP_DRIVE_STRENGTH
,
85 .dram_dqm0
= IMX6QP_DRIVE_STRENGTH
,
86 .dram_dqm1
= IMX6QP_DRIVE_STRENGTH
,
87 .dram_dqm2
= IMX6QP_DRIVE_STRENGTH
,
88 .dram_dqm3
= IMX6QP_DRIVE_STRENGTH
,
89 .dram_dqm4
= IMX6QP_DRIVE_STRENGTH
,
90 .dram_dqm5
= IMX6QP_DRIVE_STRENGTH
,
91 .dram_dqm6
= IMX6QP_DRIVE_STRENGTH
,
92 .dram_dqm7
= IMX6QP_DRIVE_STRENGTH
,
95 /* configure MX6Q/DUAL mmdc GRP io registers */
96 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs
= {
97 .grp_ddr_type
= 0x000c0000,
98 .grp_ddrmode_ctl
= 0x00020000,
99 .grp_ddrpke
= 0x00000000,
100 .grp_addds
= IMX6DQ_DRIVE_STRENGTH
,
101 .grp_ctlds
= IMX6DQ_DRIVE_STRENGTH
,
102 .grp_ddrmode
= 0x00020000,
103 .grp_b0ds
= IMX6DQ_DRIVE_STRENGTH
,
104 .grp_b1ds
= IMX6DQ_DRIVE_STRENGTH
,
105 .grp_b2ds
= IMX6DQ_DRIVE_STRENGTH
,
106 .grp_b3ds
= IMX6DQ_DRIVE_STRENGTH
,
107 .grp_b4ds
= IMX6DQ_DRIVE_STRENGTH
,
108 .grp_b5ds
= IMX6DQ_DRIVE_STRENGTH
,
109 .grp_b6ds
= IMX6DQ_DRIVE_STRENGTH
,
110 .grp_b7ds
= IMX6DQ_DRIVE_STRENGTH
,
113 /* configure MX6QP mmdc GRP io registers */
114 static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs
= {
115 .grp_ddr_type
= 0x000c0000,
116 .grp_ddrmode_ctl
= 0x00020000,
117 .grp_ddrpke
= 0x00000000,
118 .grp_addds
= IMX6QP_DRIVE_STRENGTH
,
119 .grp_ctlds
= IMX6QP_DRIVE_STRENGTH
,
120 .grp_ddrmode
= 0x00020000,
121 .grp_b0ds
= IMX6QP_DRIVE_STRENGTH
,
122 .grp_b1ds
= IMX6QP_DRIVE_STRENGTH
,
123 .grp_b2ds
= IMX6QP_DRIVE_STRENGTH
,
124 .grp_b3ds
= IMX6QP_DRIVE_STRENGTH
,
125 .grp_b4ds
= IMX6QP_DRIVE_STRENGTH
,
126 .grp_b5ds
= IMX6QP_DRIVE_STRENGTH
,
127 .grp_b6ds
= IMX6QP_DRIVE_STRENGTH
,
128 .grp_b7ds
= IMX6QP_DRIVE_STRENGTH
,
131 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
132 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs
= {
133 .dram_sdclk_0
= IMX6SDL_DRIVE_STRENGTH
,
134 .dram_sdclk_1
= IMX6SDL_DRIVE_STRENGTH
,
135 .dram_cas
= IMX6SDL_DRIVE_STRENGTH
,
136 .dram_ras
= IMX6SDL_DRIVE_STRENGTH
,
137 .dram_reset
= IMX6SDL_DRIVE_STRENGTH
,
138 .dram_sdcke0
= IMX6SDL_DRIVE_STRENGTH
,
139 .dram_sdcke1
= IMX6SDL_DRIVE_STRENGTH
,
140 .dram_sdba2
= 0x00000000,
141 .dram_sdodt0
= IMX6SDL_DRIVE_STRENGTH
,
142 .dram_sdodt1
= IMX6SDL_DRIVE_STRENGTH
,
143 .dram_sdqs0
= IMX6SDL_DRIVE_STRENGTH
,
144 .dram_sdqs1
= IMX6SDL_DRIVE_STRENGTH
,
145 .dram_sdqs2
= IMX6SDL_DRIVE_STRENGTH
,
146 .dram_sdqs3
= IMX6SDL_DRIVE_STRENGTH
,
147 .dram_sdqs4
= IMX6SDL_DRIVE_STRENGTH
,
148 .dram_sdqs5
= IMX6SDL_DRIVE_STRENGTH
,
149 .dram_sdqs6
= IMX6SDL_DRIVE_STRENGTH
,
150 .dram_sdqs7
= IMX6SDL_DRIVE_STRENGTH
,
151 .dram_dqm0
= IMX6SDL_DRIVE_STRENGTH
,
152 .dram_dqm1
= IMX6SDL_DRIVE_STRENGTH
,
153 .dram_dqm2
= IMX6SDL_DRIVE_STRENGTH
,
154 .dram_dqm3
= IMX6SDL_DRIVE_STRENGTH
,
155 .dram_dqm4
= IMX6SDL_DRIVE_STRENGTH
,
156 .dram_dqm5
= IMX6SDL_DRIVE_STRENGTH
,
157 .dram_dqm6
= IMX6SDL_DRIVE_STRENGTH
,
158 .dram_dqm7
= IMX6SDL_DRIVE_STRENGTH
,
161 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
162 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs
= {
163 .grp_ddr_type
= 0x000c0000,
164 .grp_ddrmode_ctl
= 0x00020000,
165 .grp_ddrpke
= 0x00000000,
166 .grp_addds
= IMX6SDL_DRIVE_STRENGTH
,
167 .grp_ctlds
= IMX6SDL_DRIVE_STRENGTH
,
168 .grp_ddrmode
= 0x00020000,
169 .grp_b0ds
= IMX6SDL_DRIVE_STRENGTH
,
170 .grp_b1ds
= IMX6SDL_DRIVE_STRENGTH
,
171 .grp_b2ds
= IMX6SDL_DRIVE_STRENGTH
,
172 .grp_b3ds
= IMX6SDL_DRIVE_STRENGTH
,
173 .grp_b4ds
= IMX6SDL_DRIVE_STRENGTH
,
174 .grp_b5ds
= IMX6SDL_DRIVE_STRENGTH
,
175 .grp_b6ds
= IMX6SDL_DRIVE_STRENGTH
,
176 .grp_b7ds
= IMX6SDL_DRIVE_STRENGTH
,
180 static struct mx6_ddr3_cfg h5t04g63afr
= {
194 static struct mx6_ddr3_cfg h5tq2g63dfr
= {
207 static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib
= {
208 .p0_mpwldectrl0
= 0x001f001f,
209 .p0_mpwldectrl1
= 0x001f001f,
210 .p1_mpwldectrl0
= 0x001f001f,
211 .p1_mpwldectrl1
= 0x001f001f,
212 .p0_mpdgctrl0
= 0x4301030d,
213 .p0_mpdgctrl1
= 0x03020277,
214 .p1_mpdgctrl0
= 0x4300030a,
215 .p1_mpdgctrl1
= 0x02780248,
216 .p0_mprddlctl
= 0x4536393b,
217 .p1_mprddlctl
= 0x36353441,
218 .p0_mpwrdlctl
= 0x41414743,
219 .p1_mpwrdlctl
= 0x462f453f,
223 static struct mx6_ddr_sysinfo mem_q
= {
226 /* config for full 4GB range so that get_mem_size() works */
237 .refsel
= 1, /* Refresh cycles at 32KHz */
238 .refr
= 3, /* 4 refresh commands per refresh cycle */
241 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib
= {
242 .p0_mpwldectrl0
= 0x001f001f,
243 .p0_mpwldectrl1
= 0x001f001f,
244 .p1_mpwldectrl0
= 0x001f001f,
245 .p1_mpwldectrl1
= 0x001f001f,
246 .p0_mpdgctrl0
= 0x420e020e,
247 .p0_mpdgctrl1
= 0x02000200,
248 .p1_mpdgctrl0
= 0x42020202,
249 .p1_mpdgctrl1
= 0x01720172,
250 .p0_mprddlctl
= 0x494c4f4c,
251 .p1_mprddlctl
= 0x4a4c4c49,
252 .p0_mpwrdlctl
= 0x3f3f3133,
253 .p1_mpwrdlctl
= 0x39373f2e,
256 static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib
= {
257 .p0_mpwldectrl0
= 0x0040003c,
258 .p0_mpwldectrl1
= 0x0032003e,
259 .p0_mpdgctrl0
= 0x42350231,
260 .p0_mpdgctrl1
= 0x021a0218,
261 .p0_mprddlctl
= 0x4b4b4e49,
262 .p0_mpwrdlctl
= 0x3f3f3035,
266 static struct mx6_ddr_sysinfo mem_dl
= {
269 /* config for full 4GB range so that get_mem_size() works */
280 .refsel
= 1, /* Refresh cycles at 32KHz */
281 .refr
= 3, /* 4 refresh commands per refresh cycle */
284 /* DDR 32bit 512MB */
285 static struct mx6_ddr_sysinfo mem_s
= {
288 /* config for full 4GB range so that get_mem_size() works */
299 .refsel
= 1, /* Refresh cycles at 32KHz */
300 .refr
= 3, /* 4 refresh commands per refresh cycle */
303 static void ccgr_init(void)
305 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
307 writel(0x00C03F3F, &ccm
->CCGR0
);
308 writel(0x0030FC03, &ccm
->CCGR1
);
309 writel(0x0FFFC000, &ccm
->CCGR2
);
310 writel(0x3FF03000, &ccm
->CCGR3
);
311 writel(0x00FFF300, &ccm
->CCGR4
);
312 writel(0x0F0000C3, &ccm
->CCGR5
);
313 writel(0x000003FF, &ccm
->CCGR6
);
316 static void spl_dram_init_imx6qp_lpddr3(void)
318 /* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
319 writel(0x00008000, MMDC_P0_BASE_ADDR
+ 0x01c);
320 /* Calibrations - ZQ */
321 writel(0xa1390003, MMDC_P0_BASE_ADDR
+ 0x800);
323 writel(0x00060004, MMDC_P0_BASE_ADDR
+ 0x80c);
324 writel(0x000B0004, MMDC_P0_BASE_ADDR
+ 0x810);
325 writel(0x00000004, MMDC_P1_BASE_ADDR
+ 0x80c);
326 writel(0x00000000, MMDC_P1_BASE_ADDR
+ 0x810);
328 * DQS gating, read delay, write delay calibration values
329 * based on calibration compare of 0x00ffff00
331 writel(0x03040314, MMDC_P0_BASE_ADDR
+ 0x83c);
332 writel(0x03080300, MMDC_P0_BASE_ADDR
+ 0x840);
333 writel(0x03000310, MMDC_P1_BASE_ADDR
+ 0x83c);
334 writel(0x0268023C, MMDC_P1_BASE_ADDR
+ 0x840);
335 writel(0x4034363A, MMDC_P0_BASE_ADDR
+ 0x848);
336 writel(0x36302C3C, MMDC_P1_BASE_ADDR
+ 0x848);
337 writel(0x3E3E4046, MMDC_P0_BASE_ADDR
+ 0x850);
338 writel(0x483A4844, MMDC_P1_BASE_ADDR
+ 0x850);
339 writel(0x33333333, MMDC_P0_BASE_ADDR
+ 0x81c);
340 writel(0x33333333, MMDC_P0_BASE_ADDR
+ 0x820);
341 writel(0x33333333, MMDC_P0_BASE_ADDR
+ 0x824);
342 writel(0x33333333, MMDC_P0_BASE_ADDR
+ 0x828);
343 writel(0x33333333, MMDC_P1_BASE_ADDR
+ 0x81c);
344 writel(0x33333333, MMDC_P1_BASE_ADDR
+ 0x820);
345 writel(0x33333333, MMDC_P1_BASE_ADDR
+ 0x824);
346 writel(0x33333333, MMDC_P1_BASE_ADDR
+ 0x828);
347 writel(0x24912489, MMDC_P0_BASE_ADDR
+ 0x8c0);
348 writel(0x24914452, MMDC_P1_BASE_ADDR
+ 0x8c0);
349 writel(0x00000800, MMDC_P0_BASE_ADDR
+ 0x8b8);
350 writel(0x00000800, MMDC_P1_BASE_ADDR
+ 0x8b8);
351 /* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */
352 writel(0x00020036, MMDC_P0_BASE_ADDR
+ 0x004);
353 writel(0x09444040, MMDC_P0_BASE_ADDR
+ 0x008);
354 writel(0x898E79A4, MMDC_P0_BASE_ADDR
+ 0x00c);
355 writel(0xDB538F64, MMDC_P0_BASE_ADDR
+ 0x010);
356 writel(0x01FF00DD, MMDC_P0_BASE_ADDR
+ 0x014);
357 writel(0x00011740, MMDC_P0_BASE_ADDR
+ 0x018);
358 writel(0x00008000, MMDC_P0_BASE_ADDR
+ 0x01c);
359 writel(0x000026D2, MMDC_P0_BASE_ADDR
+ 0x02c);
360 writel(0x008E1023, MMDC_P0_BASE_ADDR
+ 0x030);
361 writel(0x00000047, MMDC_P0_BASE_ADDR
+ 0x040);
362 writel(0x14420000, MMDC_P0_BASE_ADDR
+ 0x400);
363 writel(0x841A0000, MMDC_P0_BASE_ADDR
+ 0x000);
364 writel(0x00400c58, MMDC_P0_BASE_ADDR
+ 0x890);
365 /* add NOC DDR configuration */
366 writel(0x00000000, NOC_DDR_BASE_ADDR
+ 0x008);
367 writel(0x2871C39B, NOC_DDR_BASE_ADDR
+ 0x00c);
368 writel(0x000005B4, NOC_DDR_BASE_ADDR
+ 0x038);
369 writel(0x00000040, NOC_DDR_BASE_ADDR
+ 0x014);
370 writel(0x00000020, NOC_DDR_BASE_ADDR
+ 0x028);
371 writel(0x00000020, NOC_DDR_BASE_ADDR
+ 0x02c);
372 writel(0x02088032, MMDC_P0_BASE_ADDR
+ 0x01c);
373 writel(0x00008033, MMDC_P0_BASE_ADDR
+ 0x01c);
374 writel(0x00048031, MMDC_P0_BASE_ADDR
+ 0x01c);
375 writel(0x19308030, MMDC_P0_BASE_ADDR
+ 0x01c);
376 writel(0x04008040, MMDC_P0_BASE_ADDR
+ 0x01c);
377 writel(0x00007800, MMDC_P0_BASE_ADDR
+ 0x020);
378 writel(0x00022227, MMDC_P0_BASE_ADDR
+ 0x818);
379 writel(0x00022227, MMDC_P1_BASE_ADDR
+ 0x818);
380 writel(0x00025576, MMDC_P0_BASE_ADDR
+ 0x004);
381 writel(0x00011006, MMDC_P0_BASE_ADDR
+ 0x404);
382 writel(0x00000000, MMDC_P0_BASE_ADDR
+ 0x01c);
385 static void spl_dram_init(void)
388 mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs
, &mx6qp_grp_ioregs
);
389 spl_dram_init_imx6qp_lpddr3();
390 } else if (is_cpu_type(MXC_CPU_MX6SOLO
)) {
391 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
392 mx6_dram_cfg(&mem_s
, &mx6s_512m_mmdc_calib
, &h5tq2g63dfr
);
393 } else if (is_cpu_type(MXC_CPU_MX6DL
)) {
394 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
395 mx6_dram_cfg(&mem_dl
, &mx6dl_1g_mmdc_calib
, &h5tq2g63dfr
);
396 } else if (is_cpu_type(MXC_CPU_MX6Q
)) {
397 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs
, &mx6dq_grp_ioregs
);
398 mx6_dram_cfg(&mem_q
, &mx6q_2g_mmdc_calib
, &h5t04g63afr
);
404 void board_init_f(ulong dummy
)
408 /* setup AIPS and disable watchdog */
414 board_early_init_f();
419 /* UART clocks enabled and gd valid - init serial console */
420 preloader_console_init();
422 /* DDR initialization */