2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2014 O.S. Systems Software LTDA.
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/mxc_hdmi.h>
16 #include <asm/arch/sys_proto.h>
18 #include <asm/imx-common/iomux-v3.h>
19 #include <asm/imx-common/mxc_i2c.h>
20 #include <asm/imx-common/boot_mode.h>
21 #include <asm/imx-common/video.h>
23 #include <linux/sizes.h>
25 #include <fsl_esdhc.h>
33 DECLARE_GLOBAL_DATA_PTR
;
35 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
37 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
40 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
41 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
46 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
48 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
50 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
51 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
52 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
56 gd
->ram_size
= (phys_size_t
)CONFIG_DDR_MB
* 1024 * 1024;
61 static iomux_v3_cfg_t
const uart1_pads
[] = {
62 MX6_PAD_CSI0_DAT10__UART1_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
63 MX6_PAD_CSI0_DAT11__UART1_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
66 static iomux_v3_cfg_t
const usdhc1_pads
[] = {
67 MX6_PAD_SD1_CLK__SD1_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
68 MX6_PAD_SD1_CMD__SD1_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
69 MX6_PAD_SD1_DAT0__SD1_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
70 MX6_PAD_SD1_DAT1__SD1_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
71 MX6_PAD_SD1_DAT2__SD1_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
72 MX6_PAD_SD1_DAT3__SD1_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
73 /* Carrier MicroSD Card Detect */
74 MX6_PAD_GPIO_2__GPIO1_IO02
| MUX_PAD_CTRL(NO_PAD_CTRL
),
77 static iomux_v3_cfg_t
const usdhc3_pads
[] = {
78 MX6_PAD_SD3_CLK__SD3_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
79 MX6_PAD_SD3_CMD__SD3_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
80 MX6_PAD_SD3_DAT0__SD3_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
81 MX6_PAD_SD3_DAT1__SD3_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
82 MX6_PAD_SD3_DAT2__SD3_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
83 MX6_PAD_SD3_DAT3__SD3_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
84 /* SOM MicroSD Card Detect */
85 MX6_PAD_EIM_DA9__GPIO3_IO09
| MUX_PAD_CTRL(NO_PAD_CTRL
),
88 static iomux_v3_cfg_t
const enet_pads
[] = {
89 MX6_PAD_ENET_MDIO__ENET_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
90 MX6_PAD_ENET_MDC__ENET_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
91 MX6_PAD_RGMII_TXC__RGMII_TXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
92 MX6_PAD_RGMII_TD0__RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
93 MX6_PAD_RGMII_TD1__RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
94 MX6_PAD_RGMII_TD2__RGMII_TD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
95 MX6_PAD_RGMII_TD3__RGMII_TD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
96 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
97 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
98 MX6_PAD_RGMII_RXC__RGMII_RXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
99 MX6_PAD_RGMII_RD0__RGMII_RD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
100 MX6_PAD_RGMII_RD1__RGMII_RD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
101 MX6_PAD_RGMII_RD2__RGMII_RD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
102 MX6_PAD_RGMII_RD3__RGMII_RD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
103 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
104 /* AR8031 PHY Reset */
105 MX6_PAD_EIM_D29__GPIO3_IO29
| MUX_PAD_CTRL(NO_PAD_CTRL
),
108 static void setup_iomux_uart(void)
110 imx_iomux_v3_setup_multiple_pads(uart1_pads
, ARRAY_SIZE(uart1_pads
));
113 static void setup_iomux_enet(void)
115 imx_iomux_v3_setup_multiple_pads(enet_pads
, ARRAY_SIZE(enet_pads
));
117 /* Reset AR8031 PHY */
118 gpio_direction_output(ETH_PHY_RESET
, 0);
120 gpio_set_value(ETH_PHY_RESET
, 1);
123 static struct fsl_esdhc_cfg usdhc_cfg
[2] = {
128 int board_mmc_getcd(struct mmc
*mmc
)
130 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
133 switch (cfg
->esdhc_base
) {
134 case USDHC1_BASE_ADDR
:
135 ret
= !gpio_get_value(USDHC1_CD_GPIO
);
137 case USDHC3_BASE_ADDR
:
138 ret
= !gpio_get_value(USDHC3_CD_GPIO
);
145 int board_mmc_init(bd_t
*bis
)
151 * Following map is done:
152 * (U-boot device node) (Physical Port)
154 * mmc1 Carrier board MicroSD
156 for (index
= 0; index
< CONFIG_SYS_FSL_USDHC_NUM
; ++index
) {
159 imx_iomux_v3_setup_multiple_pads(
160 usdhc3_pads
, ARRAY_SIZE(usdhc3_pads
));
161 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
162 usdhc_cfg
[0].max_bus_width
= 4;
163 gpio_direction_input(USDHC3_CD_GPIO
);
166 imx_iomux_v3_setup_multiple_pads(
167 usdhc1_pads
, ARRAY_SIZE(usdhc1_pads
));
168 usdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC_CLK
);
169 usdhc_cfg
[1].max_bus_width
= 4;
170 gpio_direction_input(USDHC1_CD_GPIO
);
173 printf("Warning: you configured more USDHC controllers"
174 "(%d) then supported by the board (%d)\n",
175 index
+ 1, CONFIG_SYS_FSL_USDHC_NUM
);
179 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[index
]);
187 static int mx6_rgmii_rework(struct phy_device
*phydev
)
191 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
192 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xd, 0x7);
193 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xe, 0x8016);
194 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xd, 0x4007);
196 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, 0xe);
199 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xe, val
);
201 /* introduce tx clock delay */
202 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1d, 0x5);
203 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, 0x1e);
205 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, val
);
210 int board_phy_config(struct phy_device
*phydev
)
212 mx6_rgmii_rework(phydev
);
214 if (phydev
->drv
->config
)
215 phydev
->drv
->config(phydev
);
220 #if defined(CONFIG_VIDEO_IPUV3)
221 struct i2c_pads_info i2c2_pad_info
= {
223 .i2c_mode
= MX6_PAD_KEY_COL3__I2C2_SCL
224 | MUX_PAD_CTRL(I2C_PAD_CTRL
),
225 .gpio_mode
= MX6_PAD_KEY_COL3__GPIO4_IO12
226 | MUX_PAD_CTRL(I2C_PAD_CTRL
),
227 .gp
= IMX_GPIO_NR(4, 12)
230 .i2c_mode
= MX6_PAD_KEY_ROW3__I2C2_SDA
231 | MUX_PAD_CTRL(I2C_PAD_CTRL
),
232 .gpio_mode
= MX6_PAD_KEY_ROW3__GPIO4_IO13
233 | MUX_PAD_CTRL(I2C_PAD_CTRL
),
234 .gp
= IMX_GPIO_NR(4, 13)
238 static iomux_v3_cfg_t
const fwadapt_7wvga_pads
[] = {
239 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK
,
240 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02
, /* HSync */
241 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03
, /* VSync */
242 MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04
243 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm
), /* Contrast */
244 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15
, /* DISP0_DRDY */
246 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00
,
247 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01
,
248 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02
,
249 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03
,
250 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04
,
251 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05
,
252 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06
,
253 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07
,
254 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08
,
255 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09
,
256 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10
,
257 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11
,
258 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12
,
259 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13
,
260 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14
,
261 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15
,
262 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16
,
263 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17
,
265 MX6_PAD_SD4_DAT2__GPIO2_IO10
266 | MUX_PAD_CTRL(NO_PAD_CTRL
), /* DISP0_BKLEN */
267 MX6_PAD_SD4_DAT3__GPIO2_IO11
268 | MUX_PAD_CTRL(NO_PAD_CTRL
), /* DISP0_VDDEN */
271 static void do_enable_hdmi(struct display_info_t
const *dev
)
273 imx_enable_hdmi_phy();
276 static int detect_i2c(struct display_info_t
const *dev
)
278 return (0 == i2c_set_bus_num(dev
->bus
)) &&
279 (0 == i2c_probe(dev
->addr
));
282 static void enable_fwadapt_7wvga(struct display_info_t
const *dev
)
284 imx_iomux_v3_setup_multiple_pads(
286 ARRAY_SIZE(fwadapt_7wvga_pads
));
288 gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
289 gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
292 struct display_info_t
const displays
[] = {{
295 .pixfmt
= IPU_PIX_FMT_RGB24
,
296 .detect
= detect_hdmi
,
297 .enable
= do_enable_hdmi
,
311 .vmode
= FB_VMODE_NONINTERLACED
315 .pixfmt
= IPU_PIX_FMT_RGB666
,
316 .detect
= detect_i2c
,
317 .enable
= enable_fwadapt_7wvga
,
319 .name
= "FWBADAPT-LCD-F07A-0102",
331 .vmode
= FB_VMODE_NONINTERLACED
333 size_t display_count
= ARRAY_SIZE(displays
);
335 static void setup_display(void)
337 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
343 reg
= readl(&mxc_ccm
->chsccdr
);
344 reg
|= (CHSCCDR_CLK_SEL_LDB_DI0
345 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET
);
346 writel(reg
, &mxc_ccm
->chsccdr
);
348 /* Disable LCD backlight */
349 imx_iomux_v3_setup_pad(MX6_PAD_DI0_PIN4__GPIO4_IO20
);
350 gpio_direction_input(IMX_GPIO_NR(4, 20));
352 #endif /* CONFIG_VIDEO_IPUV3 */
354 int board_eth_init(bd_t
*bis
)
358 return cpu_eth_init(bis
);
361 int board_early_init_f(void)
364 #if defined(CONFIG_VIDEO_IPUV3)
371 * Do not overwrite the console
372 * Use always serial for U-Boot console
374 int overwrite_console(void)
379 #ifdef CONFIG_CMD_BMODE
380 static const struct boot_mode board_boot_modes
[] = {
381 /* 4 bit bus width */
382 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
383 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
388 int board_late_init(void)
390 #ifdef CONFIG_CMD_BMODE
391 add_board_boot_modes(board_boot_modes
);
399 /* address of boot parameters */
400 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
402 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c2_pad_info
);
409 puts("Board: Wandboard\n");