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git.ipfire.org Git - people/ms/u-boot.git/blob - board/xilinx/common/xipif_v1_23_b.h
1 /* $Id: xipif_v1_23_b.h,v 1.1 2002/03/18 23:24:52 linnj Exp $ */
2 /******************************************************************************
4 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
5 * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
6 * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
7 * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
8 * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
9 * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
10 * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
11 * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
12 * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
13 * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
14 * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
15 * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
16 * FOR A PARTICULAR PURPOSE.
18 * (c) Copyright 2002 Xilinx Inc.
19 * All rights reserved.
21 ******************************************************************************/
22 /******************************************************************************
30 * The XIpIf component encapsulates the IPIF, which is the standard interface
31 * that IP must adhere to when connecting to a bus. The purpose of this
32 * component is to encapsulate the IPIF processing such that maintainability
33 * is increased. This component does not provide a lot of abstraction from
34 * from the details of the IPIF as it is considered a building block for
35 * device drivers. A device driver designer must be familiar with the
36 * details of the IPIF hardware to use this component.
38 * The IPIF hardware provides a building block for all hardware devices such
39 * that each device does not need to reimplement these building blocks. The
40 * IPIF contains other building blocks, such as FIFOs and DMA channels, which
41 * are also common to many devices. These blocks are implemented as separate
42 * hardware blocks and instantiated within the IPIF. The primary hardware of
43 * the IPIF which is implemented by this software component is the interrupt
44 * architecture. Since there are many blocks of a device which may generate
45 * interrupts, all the interrupt processing is contained in the common part
46 * of the device, the IPIF. This interrupt processing is for the device level
47 * only and does not include any processing for the interrupt controller.
49 * A device is a mechanism such as an Ethernet MAC. The device is made
50 * up of several parts which include an IPIF and the IP. The IPIF contains most
51 * of the device infrastructure which is common to all devices, such as
52 * interrupt processing, DMA channels, and FIFOs. The infrastructure may also
53 * be referred to as IPIF internal blocks since they are part of the IPIF and
54 * are separate blocks that can be selected based upon the needs of the device.
55 * The IP of the device is the logic that is unique to the device and interfaces
56 * to the IPIF of the device.
58 * In general, there are two levels of registers within the IPIF. The first
59 * level, referred to as the device level, contains registers which are for the
60 * entire device. The second level, referred to as the IP level, contains
61 * registers which are specific to the IP of the device. The two levels of
62 * registers are designed to be hierarchical such that the device level is
63 * is a more general register set above the more specific registers of the IP.
64 * The IP level of registers provides functionality which is typically common
65 * across all devices and allows IP designers to focus on the unique aspects
70 * It is the responsibility of the device driver designer to use critical
71 * sections as necessary when calling functions of the IPIF. This component
72 * does not use critical sections and it does access registers using
73 * read-modify-write operations. Calls to IPIF functions from a main thread
74 * and from an interrupt context could produce unpredictable behavior such that
75 * the caller must provide the appropriate critical sections.
79 * The functions of the IPIF are not thread safe such that the caller of all
80 * functions is responsible for ensuring mutual exclusion for an IPIF. Mutual
81 * exclusion across multiple IPIF components is not necessary.
87 * MODIFICATION HISTORY:
89 * Ver Who Date Changes
90 * ----- ---- -------- -----------------------------------------------
91 * 1.23b jhl 02/27/01 Repartioned to minimize size
93 ******************************************************************************/
95 #ifndef XIPIF_H /* prevent circular inclusions */
96 #define XIPIF_H /* by using protection macros */
98 /***************************** Include Files *********************************/
99 #include "xbasic_types.h"
101 #include "xversion.h"
103 /************************** Constant Definitions *****************************/
105 /* the following constants define the register offsets for the registers of the
106 * IPIF, there are some holes in the memory map for reserved addresses to allow
107 * other registers to be added and still match the memory map of the interrupt
108 * controller registers
110 #define XIIF_V123B_DISR_OFFSET 0UL /* device interrupt status register */
111 #define XIIF_V123B_DIPR_OFFSET 4UL /* device interrupt pending register */
112 #define XIIF_V123B_DIER_OFFSET 8UL /* device interrupt enable register */
113 #define XIIF_V123B_DIIR_OFFSET 24UL /* device interrupt ID register */
114 #define XIIF_V123B_DGIER_OFFSET 28UL /* device global interrupt enable reg */
115 #define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */
116 #define XIIF_V123B_IIER_OFFSET 40UL /* IP interrupt enable register */
117 #define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */
119 #define XIIF_V123B_RESET_MASK 0xAUL
121 /* the following constant is used for the device global interrupt enable
122 * register, to enable all interrupts for the device, this is the only bit
125 #define XIIF_V123B_GINTR_ENABLE_MASK 0x80000000UL
127 /* the following constants contain the masks to identify each internal IPIF
128 * condition in the device registers of the IPIF, interrupts are assigned
129 * in the register from LSB to the MSB
131 #define XIIF_V123B_ERROR_MASK 1UL /* LSB of the register */
133 /* The following constants contain interrupt IDs which identify each internal
134 * IPIF condition, this value must correlate with the mask constant for the
137 #define XIIF_V123B_ERROR_INTERRUPT_ID 0 /* interrupt bit #, (LSB = 0) */
138 #define XIIF_V123B_NO_INTERRUPT_ID 128 /* no interrupts are pending */
140 /**************************** Type Definitions *******************************/
142 /***************** Macros (Inline Functions) Definitions *********************/
144 /******************************************************************************
152 * Reset the IPIF component and hardware. This is a destructive operation that
153 * could cause the loss of data since resetting the IPIF of a device also
154 * resets the device using the IPIF and any blocks, such as FIFOs or DMA
155 * channels, within the IPIF. All registers of the IPIF will contain their
156 * reset value when this function returns.
160 * RegBaseAddress contains the base address of the IPIF registers.
170 ******************************************************************************/
172 /* the following constant is used in the reset register to cause the IPIF to
175 #define XIIF_V123B_RESET(RegBaseAddress) \
176 XIo_Out32(RegBaseAddress + XIIF_V123B_RESETR_OFFSET, XIIF_V123B_RESET_MASK)
178 /******************************************************************************
182 * XIIF_V123B_WRITE_DISR
186 * This function sets the device interrupt status register to the value.
187 * This register indicates the status of interrupt sources for a device
188 * which contains the IPIF. The status is independent of whether interrupts
189 * are enabled and could be used for polling a device at a higher level rather
190 * than a more detailed level.
192 * Each bit of the register correlates to a specific interrupt source within the
193 * device which contains the IPIF. With the exception of some internal IPIF
194 * conditions, the contents of this register are not latched but indicate
195 * the live status of the interrupt sources within the device. Writing any of
196 * the non-latched bits of the register will have no effect on the register.
198 * For the latched bits of this register only, setting a bit which is zero
199 * within this register causes an interrupt to generated. The device global
200 * interrupt enable register and the device interrupt enable register must be set
201 * appropriately to allow an interrupt to be passed out of the device. The
202 * interrupt is cleared by writing to this register with the bits to be
203 * cleared set to a one and all others to zero. This register implements a
204 * toggle on write functionality meaning any bits which are set in the value
205 * written cause the bits in the register to change to the opposite state.
207 * This function writes the specified value to the register such that
208 * some bits may be set and others cleared. It is the caller's responsibility
209 * to get the value of the register prior to setting the value to prevent a
210 * destructive behavior.
214 * RegBaseAddress contains the base address of the IPIF registers.
216 * Status contains the value to be written to the interrupt status register of
217 * the device. The only bits which can be written are the latched bits which
218 * contain the internal IPIF conditions. The following values may be used to
219 * set the status register or clear an interrupt condition.
221 * XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
231 ******************************************************************************/
232 #define XIIF_V123B_WRITE_DISR(RegBaseAddress, Status) \
233 XIo_Out32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET, (Status))
235 /******************************************************************************
239 * XIIF_V123B_READ_DISR
243 * This function gets the device interrupt status register contents.
244 * This register indicates the status of interrupt sources for a device
245 * which contains the IPIF. The status is independent of whether interrupts
246 * are enabled and could be used for polling a device at a higher level.
248 * Each bit of the register correlates to a specific interrupt source within the
249 * device which contains the IPIF. With the exception of some internal IPIF
250 * conditions, the contents of this register are not latched but indicate
251 * the live status of the interrupt sources within the device.
253 * For only the latched bits of this register, the interrupt may be cleared by
254 * writing to these bits in the status register.
258 * RegBaseAddress contains the base address of the IPIF registers.
262 * A status which contains the value read from the interrupt status register of
263 * the device. The bit definitions are specific to the device with
264 * the exception of the latched internal IPIF condition bits. The following
265 * values may be used to detect internal IPIF conditions in the status.
267 * XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
273 ******************************************************************************/
274 #define XIIF_V123B_READ_DISR(RegBaseAddress) \
275 XIo_In32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET)
277 /******************************************************************************
281 * XIIF_V123B_WRITE_DIER
285 * This function sets the device interrupt enable register contents.
286 * This register controls which interrupt sources of the device are allowed to
287 * generate an interrupt. The device global interrupt enable register must also
288 * be set appropriately for an interrupt to be passed out of the device.
290 * Each bit of the register correlates to a specific interrupt source within the
291 * device which contains the IPIF. Setting a bit in this register enables that
292 * interrupt source to generate an interrupt. Clearing a bit in this register
293 * disables interrupt generation for that interrupt source.
295 * This function writes only the specified value to the register such that
296 * some interrupts source may be enabled and others disabled. It is the
297 * caller's responsibility to get the value of the interrupt enable register
298 * prior to setting the value to prevent an destructive behavior.
300 * An interrupt source may not be enabled to generate an interrupt, but can
301 * still be polled in the interrupt status register.
305 * RegBaseAddress contains the base address of the IPIF registers.
307 * Enable contains the value to be written to the interrupt enable register
308 * of the device. The bit definitions are specific to the device with
309 * the exception of the internal IPIF conditions. The following
310 * values may be used to enable the internal IPIF conditions interrupts.
312 * XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
320 * Signature: u32 XIIF_V123B_WRITE_DIER(u32 RegBaseAddress,
323 ******************************************************************************/
324 #define XIIF_V123B_WRITE_DIER(RegBaseAddress, Enable) \
325 XIo_Out32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET, (Enable))
327 /******************************************************************************
331 * XIIF_V123B_READ_DIER
335 * This function gets the device interrupt enable register contents.
336 * This register controls which interrupt sources of the device
337 * are allowed to generate an interrupt. The device global interrupt enable
338 * register and the device interrupt enable register must also be set
339 * appropriately for an interrupt to be passed out of the device.
341 * Each bit of the register correlates to a specific interrupt source within the
342 * device which contains the IPIF. Setting a bit in this register enables that
343 * interrupt source to generate an interrupt if the global enable is set
344 * appropriately. Clearing a bit in this register disables interrupt generation
345 * for that interrupt source regardless of the global interrupt enable.
349 * RegBaseAddress contains the base address of the IPIF registers.
353 * The value read from the interrupt enable register of the device. The bit
354 * definitions are specific to the device with the exception of the internal
355 * IPIF conditions. The following values may be used to determine from the
356 * value if the internal IPIF conditions interrupts are enabled.
358 * XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
364 ******************************************************************************/
365 #define XIIF_V123B_READ_DIER(RegBaseAddress) \
366 XIo_In32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET)
368 /******************************************************************************
372 * XIIF_V123B_READ_DIPR
376 * This function gets the device interrupt pending register contents.
377 * This register indicates the pending interrupt sources, those that are waiting
378 * to be serviced by the software, for a device which contains the IPIF.
379 * An interrupt must be enabled in the interrupt enable register of the IPIF to
382 * Each bit of the register correlates to a specific interrupt source within the
383 * the device which contains the IPIF. With the exception of some internal IPIF
384 * conditions, the contents of this register are not latched since the condition
385 * is latched in the IP interrupt status register, by an internal block of the
386 * IPIF such as a FIFO or DMA channel, or by the IP of the device. This register
387 * is read only and is not latched, but it is necessary to acknowledge (clear)
388 * the interrupt condition by performing the appropriate processing for the IP
389 * or block within the IPIF.
391 * This register can be thought of as the contents of the interrupt status
392 * register ANDed with the contents of the interrupt enable register.
396 * RegBaseAddress contains the base address of the IPIF registers.
400 * The value read from the interrupt pending register of the device. The bit
401 * definitions are specific to the device with the exception of the latched
402 * internal IPIF condition bits. The following values may be used to detect
403 * internal IPIF conditions in the value.
405 * XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
411 ******************************************************************************/
412 #define XIIF_V123B_READ_DIPR(RegBaseAddress) \
413 XIo_In32((RegBaseAddress) + XIIF_V123B_DIPR_OFFSET)
415 /******************************************************************************
419 * XIIF_V123B_READ_DIIR
423 * This function gets the device interrupt ID for the highest priority interrupt
424 * which is pending from the interrupt ID register. This function provides
425 * priority resolution such that faster interrupt processing is possible.
426 * Without priority resolution, it is necessary for the software to read the
427 * interrupt pending register and then check each interrupt source to determine
428 * if an interrupt is pending. Priority resolution becomes more important as the
429 * number of interrupt sources becomes larger.
431 * Interrupt priorities are based upon the bit position of the interrupt in the
432 * interrupt pending register with bit 0 being the highest priority. The
433 * interrupt ID is the priority of the interrupt, 0 - 31, with 0 being the
434 * highest priority. The interrupt ID register is live rather than latched such
435 * that multiple calls to this function may not yield the same results. A
436 * special value, outside of the interrupt priority range of 0 - 31, is
437 * contained in the register which indicates that no interrupt is pending. This
438 * may be useful for allowing software to continue processing interrupts in a
439 * loop until there are no longer any interrupts pending.
441 * The interrupt ID is designed to allow a function pointer table to be used
442 * in the software such that the interrupt ID is used as an index into that
443 * table. The function pointer table could contain an instance pointer, such
444 * as to DMA channel, and a function pointer to the function which handles
445 * that interrupt. This design requires the interrupt processing of the device
446 * driver to be partitioned into smaller more granular pieces based upon
447 * hardware used by the device, such as DMA channels and FIFOs.
449 * It is not mandatory that this function be used by the device driver software.
450 * It may choose to read the pending register and resolve the pending interrupt
451 * priorities on it's own.
455 * RegBaseAddress contains the base address of the IPIF registers.
459 * An interrupt ID, 0 - 31, which identifies the highest priority interrupt
460 * which is pending. A value of XIIF_NO_INTERRUPT_ID indicates that there is
461 * no interrupt pending. The following values may be used to identify the
462 * interrupt ID for the internal IPIF interrupts.
464 * XIIF_V123B_ERROR_INTERRUPT_ID Indicates a device error in the IPIF
470 ******************************************************************************/
471 #define XIIF_V123B_READ_DIIR(RegBaseAddress) \
472 XIo_In32((RegBaseAddress) + XIIF_V123B_DIIR_OFFSET)
474 /******************************************************************************
478 * XIIF_V123B_GLOBAL_INTR_DISABLE
482 * This function disables all interrupts for the device by writing to the global
483 * interrupt enable register. This register provides the ability to disable
484 * interrupts without any modifications to the interrupt enable register such
485 * that it is minimal effort to restore the interrupts to the previous enabled
486 * state. The corresponding function, XIpIf_GlobalIntrEnable, is provided to
487 * restore the interrupts to the previous enabled state. This function is
488 * designed to be used in critical sections of device drivers such that it is
489 * not necessary to disable other device interrupts.
493 * RegBaseAddress contains the base address of the IPIF registers.
503 ******************************************************************************/
504 #define XIIF_V123B_GINTR_DISABLE(RegBaseAddress) \
505 XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, 0)
507 /******************************************************************************
511 * XIIF_V123B_GINTR_ENABLE
515 * This function writes to the global interrupt enable register to enable
516 * interrupts from the device. This register provides the ability to enable
517 * interrupts without any modifications to the interrupt enable register such
518 * that it is minimal effort to restore the interrupts to the previous enabled
519 * state. This function does not enable individual interrupts as the interrupt
520 * enable register must be set appropriately. This function is designed to be
521 * used in critical sections of device drivers such that it is not necessary to
522 * disable other device interrupts.
526 * RegBaseAddress contains the base address of the IPIF registers.
536 ******************************************************************************/
537 #define XIIF_V123B_GINTR_ENABLE(RegBaseAddress) \
538 XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, \
539 XIIF_V123B_GINTR_ENABLE_MASK)
541 /******************************************************************************
545 * XIIF_V123B_IS_GINTR_ENABLED
549 * This function determines if interrupts are enabled at the global level by
550 * reading the gloabl interrupt register. This register provides the ability to
551 * disable interrupts without any modifications to the interrupt enable register
552 * such that it is minimal effort to restore the interrupts to the previous
557 * RegBaseAddress contains the base address of the IPIF registers.
561 * XTRUE if interrupts are enabled for the IPIF, XFALSE otherwise.
567 ******************************************************************************/
568 #define XIIF_V123B_IS_GINTR_ENABLED(RegBaseAddress) \
569 (XIo_In32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET) == \
570 XIIF_V123B_GINTR_ENABLE_MASK)
572 /******************************************************************************
576 * XIIF_V123B_WRITE_IISR
580 * This function sets the IP interrupt status register to the specified value.
581 * This register indicates the status of interrupt sources for the IP of the
582 * device. The IP is defined as the part of the device that connects to the
583 * IPIF. The status is independent of whether interrupts are enabled such that
584 * the status register may also be polled when interrupts are not enabled.
586 * Each bit of the register correlates to a specific interrupt source within the
587 * IP. All bits of this register are latched. Setting a bit which is zero
588 * within this register causes an interrupt to be generated. The device global
589 * interrupt enable register and the device interrupt enable register must be set
590 * appropriately to allow an interrupt to be passed out of the device. The
591 * interrupt is cleared by writing to this register with the bits to be
592 * cleared set to a one and all others to zero. This register implements a
593 * toggle on write functionality meaning any bits which are set in the value
594 * written cause the bits in the register to change to the opposite state.
596 * This function writes only the specified value to the register such that
597 * some status bits may be set and others cleared. It is the caller's
598 * responsibility to get the value of the register prior to setting the value
599 * to prevent an destructive behavior.
603 * RegBaseAddress contains the base address of the IPIF registers.
605 * Status contains the value to be written to the IP interrupt status
606 * register. The bit definitions are specific to the device IP.
616 ******************************************************************************/
617 #define XIIF_V123B_WRITE_IISR(RegBaseAddress, Status) \
618 XIo_Out32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET, (Status))
620 /******************************************************************************
624 * XIIF_V123B_READ_IISR
628 * This function gets the contents of the IP interrupt status register.
629 * This register indicates the status of interrupt sources for the IP of the
630 * device. The IP is defined as the part of the device that connects to the
631 * IPIF. The status is independent of whether interrupts are enabled such
632 * that the status register may also be polled when interrupts are not enabled.
634 * Each bit of the register correlates to a specific interrupt source within the
635 * device. All bits of this register are latched. Writing a 1 to a bit within
636 * this register causes an interrupt to be generated if enabled in the interrupt
637 * enable register and the global interrupt enable is set. Since the status is
638 * latched, each status bit must be acknowledged in order for the bit in the
639 * status register to be updated. Each bit can be acknowledged by writing a
640 * 0 to the bit in the status register.
644 * RegBaseAddress contains the base address of the IPIF registers.
648 * A status which contains the value read from the IP interrupt status register.
649 * The bit definitions are specific to the device IP.
655 ******************************************************************************/
656 #define XIIF_V123B_READ_IISR(RegBaseAddress) \
657 XIo_In32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET)
659 /******************************************************************************
663 * XIIF_V123B_WRITE_IIER
667 * This function sets the IP interrupt enable register contents. This register
668 * controls which interrupt sources of the IP are allowed to generate an
669 * interrupt. The global interrupt enable register and the device interrupt
670 * enable register must also be set appropriately for an interrupt to be
671 * passed out of the device containing the IPIF and the IP.
673 * Each bit of the register correlates to a specific interrupt source within the
674 * IP. Setting a bit in this register enables the interrupt source to generate
675 * an interrupt. Clearing a bit in this register disables interrupt generation
676 * for that interrupt source.
678 * This function writes only the specified value to the register such that
679 * some interrupt sources may be enabled and others disabled. It is the
680 * caller's responsibility to get the value of the interrupt enable register
681 * prior to setting the value to prevent an destructive behavior.
685 * RegBaseAddress contains the base address of the IPIF registers.
687 * Enable contains the value to be written to the IP interrupt enable register.
688 * The bit definitions are specific to the device IP.
698 ******************************************************************************/
699 #define XIIF_V123B_WRITE_IIER(RegBaseAddress, Enable) \
700 XIo_Out32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET, (Enable))
702 /******************************************************************************
706 * XIIF_V123B_READ_IIER
711 * This function gets the IP interrupt enable register contents. This register
712 * controls which interrupt sources of the IP are allowed to generate an
713 * interrupt. The global interrupt enable register and the device interrupt
714 * enable register must also be set appropriately for an interrupt to be
715 * passed out of the device containing the IPIF and the IP.
717 * Each bit of the register correlates to a specific interrupt source within the
718 * IP. Setting a bit in this register enables the interrupt source to generate
719 * an interrupt. Clearing a bit in this register disables interrupt generation
720 * for that interrupt source.
724 * RegBaseAddress contains the base address of the IPIF registers.
728 * The contents read from the IP interrupt enable register. The bit definitions
729 * are specific to the device IP.
733 * Signature: u32 XIIF_V123B_READ_IIER(u32 RegBaseAddress)
735 ******************************************************************************/
736 #define XIIF_V123B_READ_IIER(RegBaseAddress) \
737 XIo_In32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET)
739 /************************** Function Prototypes ******************************/
742 * Initialization Functions
744 XStatus
XIpIfV123b_SelfTest(u32 RegBaseAddress
, u8 IpRegistersWidth
);
746 #endif /* end of protection macro */