1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/psu_init_gpl.h>
19 #include <dm/device.h>
20 #include <dm/uclass.h>
22 #include <dwc3-uboot.h>
25 #include <linux/sizes.h>
27 #include "pm_cfg_obj.h"
29 DECLARE_GLOBAL_DATA_PTR
;
31 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
32 !defined(CONFIG_SPL_BUILD)
33 static xilinx_desc zynqmppl
= XILINX_ZYNQMP_DESC
;
40 } zynqmp_devices
[] = {
132 { /* For testing purpose only */
180 int chip_id(unsigned char id
)
185 if (current_el() != 3) {
186 regs
.regs
[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID
;
195 * regs[0][31:0] = status of the operation
196 * regs[0][63:32] = CSU.IDCODE register
197 * regs[1][31:0] = CSU.version register
198 * regs[1][63:32] = CSU.IDCODE2 register
202 regs
.regs
[0] = upper_32_bits(regs
.regs
[0]);
203 regs
.regs
[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK
|
204 ZYNQMP_CSU_IDCODE_SVD_MASK
;
205 regs
.regs
[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT
;
209 regs
.regs
[1] = lower_32_bits(regs
.regs
[1]);
210 regs
.regs
[1] &= ZYNQMP_CSU_SILICON_VER_MASK
;
214 regs
.regs
[1] = lower_32_bits(regs
.regs
[1]);
215 regs
.regs
[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT
;
219 printf("%s, Invalid Req:0x%x\n", __func__
, id
);
224 val
= readl(ZYNQMP_CSU_IDCODE_ADDR
);
225 val
&= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK
|
226 ZYNQMP_CSU_IDCODE_SVD_MASK
;
227 val
>>= ZYNQMP_CSU_IDCODE_SVD_SHIFT
;
230 val
= readl(ZYNQMP_CSU_VER_ADDR
);
231 val
&= ZYNQMP_CSU_SILICON_VER_MASK
;
234 printf("%s, Invalid Req:0x%x\n", __func__
, id
);
241 #define ZYNQMP_VERSION_SIZE 9
242 #define ZYNQMP_PL_STATUS_BIT 9
243 #define ZYNQMP_IPDIS_VCU_BIT 8
244 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
245 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
246 #define ZYNQMP_CSU_VCUDIS_VER_MASK ZYNQMP_CSU_VERSION_MASK & \
247 ~BIT(ZYNQMP_IPDIS_VCU_BIT)
248 #define MAX_VARIANTS_EV 3
250 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
251 !defined(CONFIG_SPL_BUILD)
252 static char *zynqmp_get_silicon_idcode_name(void)
256 static char name
[ZYNQMP_VERSION_SIZE
];
258 id
= chip_id(IDCODE
);
259 ver
= chip_id(IDCODE2
);
261 for (i
= 0; i
< ARRAY_SIZE(zynqmp_devices
); i
++) {
262 if (zynqmp_devices
[i
].id
== id
) {
263 if (zynqmp_devices
[i
].evexists
&&
264 !(ver
& ZYNQMP_PL_STATUS_MASK
))
266 if (zynqmp_devices
[i
].ver
== (ver
&
267 ZYNQMP_CSU_VERSION_MASK
))
272 if (i
>= ARRAY_SIZE(zynqmp_devices
))
275 strncat(name
, "zu", 2);
276 if (!zynqmp_devices
[i
].evexists
||
277 (ver
& ZYNQMP_PL_STATUS_MASK
)) {
278 strncat(name
, zynqmp_devices
[i
].name
,
279 ZYNQMP_VERSION_SIZE
- 3);
284 * Here we are means, PL not powered up and ev variant
285 * exists. So, we need to ignore VCU disable bit(8) in
286 * version and findout if its CG or EG/EV variant.
288 for (j
= 0; j
< MAX_VARIANTS_EV
; j
++, i
++) {
289 if ((zynqmp_devices
[i
].ver
& ~BIT(ZYNQMP_IPDIS_VCU_BIT
)) ==
290 (ver
& ZYNQMP_CSU_VCUDIS_VER_MASK
)) {
291 strncat(name
, zynqmp_devices
[i
].name
,
292 ZYNQMP_VERSION_SIZE
- 3);
297 if (j
>= MAX_VARIANTS_EV
)
300 if (strstr(name
, "eg") || strstr(name
, "ev")) {
301 buf
= strstr(name
, "e");
309 int board_early_init_f(void)
312 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
315 pm_api_version
= zynqmp_pmufw_version();
316 printf("PMUFW:\tv%d.%d\n",
317 pm_api_version
>> ZYNQMP_PM_VERSION_MAJOR_SHIFT
,
318 pm_api_version
& ZYNQMP_PM_VERSION_MINOR_MASK
);
320 if (pm_api_version
< ZYNQMP_PM_VERSION
)
321 panic("PMUFW version error. Expected: v%d.%d\n",
322 ZYNQMP_PM_VERSION_MAJOR
, ZYNQMP_PM_VERSION_MINOR
);
325 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
334 #if defined(CONFIG_SPL_BUILD)
335 /* Check *at build time* if the filename is an non-empty string */
336 if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE
) > 1)
337 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj
,
338 zynqmp_pm_cfg_obj_size
);
341 printf("EL Level:\tEL%d\n", current_el());
343 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
344 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
345 defined(CONFIG_SPL_BUILD))
346 if (current_el() != 3) {
347 zynqmppl
.name
= zynqmp_get_silicon_idcode_name();
348 printf("Chip ID:\t%s\n", zynqmppl
.name
);
350 fpga_add(fpga_xilinx
, &zynqmppl
);
357 int board_early_init_r(void)
361 if (current_el() != 3)
364 val
= readl(&crlapb_base
->timestamp_ref_ctrl
);
365 val
&= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT
;
368 val
= readl(&crlapb_base
->timestamp_ref_ctrl
);
369 val
|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT
;
370 writel(val
, &crlapb_base
->timestamp_ref_ctrl
);
372 /* Program freq register in System counter */
373 writel(zynqmp_get_system_timer_freq(),
374 &iou_scntr_secure
->base_frequency_id_register
);
375 /* And enable system counter */
376 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN
,
377 &iou_scntr_secure
->counter_control_register
);
382 unsigned long do_go_exec(ulong (*entry
)(int, char * const []), int argc
,
387 if (current_el() > 1) {
390 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry
,
393 printf("FAIL: current EL is not above EL1\n");
399 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
400 int dram_init_banksize(void)
404 ret
= fdtdec_setup_memory_banksize();
415 if (fdtdec_setup_mem_size_base() != 0)
421 int dram_init_banksize(void)
423 #if defined(CONFIG_NR_DRAM_BANKS)
424 gd
->bd
->bi_dram
[0].start
= CONFIG_SYS_SDRAM_BASE
;
425 gd
->bd
->bi_dram
[0].size
= get_effective_memsize();
435 gd
->ram_size
= get_ram_size((void *)CONFIG_SYS_SDRAM_BASE
,
436 CONFIG_SYS_SDRAM_SIZE
);
442 void reset_cpu(ulong addr
)
446 #if defined(CONFIG_BOARD_LATE_INIT)
447 static const struct {
450 } reset_reasons
[] = {
451 { RESET_REASON_DEBUG_SYS
, "DEBUG" },
452 { RESET_REASON_SOFT
, "SOFT" },
453 { RESET_REASON_SRST
, "SRST" },
454 { RESET_REASON_PSONLY
, "PS-ONLY" },
455 { RESET_REASON_PMU
, "PMU" },
456 { RESET_REASON_INTERNAL
, "INTERNAL" },
457 { RESET_REASON_EXTERNAL
, "EXTERNAL" },
461 static int reset_reason(void)
465 const char *reason
= NULL
;
467 ret
= zynqmp_mmio_read((ulong
)&crlapb_base
->reset_reason
, ®
);
471 puts("Reset reason:\t");
473 for (i
= 0; i
< ARRAY_SIZE(reset_reasons
); i
++) {
474 if (reg
& reset_reasons
[i
].bit
) {
475 reason
= reset_reasons
[i
].name
;
476 printf("%s ", reset_reasons
[i
].name
);
483 env_set("reset_reason", reason
);
485 ret
= zynqmp_mmio_write(~0, ~0, (ulong
)&crlapb_base
->reset_reason
);
492 static int set_fdtfile(void)
494 char *compatible
, *fdtfile
;
495 const char *suffix
= ".dtb";
496 const char *vendor
= "xilinx/";
498 if (env_get("fdtfile"))
501 compatible
= (char *)fdt_getprop(gd
->fdt_blob
, 0, "compatible", NULL
);
503 debug("Compatible: %s\n", compatible
);
505 /* Discard vendor prefix */
506 strsep(&compatible
, ",");
508 fdtfile
= calloc(1, strlen(vendor
) + strlen(compatible
) +
513 sprintf(fdtfile
, "%s%s%s", vendor
, compatible
, suffix
);
515 env_set("fdtfile", fdtfile
);
522 int board_late_init(void)
529 int env_targets_len
= 0;
536 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
540 if (!(gd
->flags
& GD_FLG_ENV_DEFAULT
)) {
541 debug("Saved variables - Skipping\n");
549 ret
= zynqmp_mmio_read((ulong
)&crlapb_base
->boot_mode
, ®
);
553 if (reg
>> BOOT_MODE_ALT_SHIFT
)
554 reg
>>= BOOT_MODE_ALT_SHIFT
;
556 bootmode
= reg
& BOOT_MODES_MASK
;
563 env_set("modeboot", "usb_dfu_spl");
568 env_set("modeboot", "jtagboot");
570 case QSPI_MODE_24BIT
:
571 case QSPI_MODE_32BIT
:
574 env_set("modeboot", "qspiboot");
579 env_set("modeboot", "emmcboot");
583 if (uclass_get_device_by_name(UCLASS_MMC
,
584 "mmc@ff160000", &dev
) &&
585 uclass_get_device_by_name(UCLASS_MMC
,
586 "sdhci@ff160000", &dev
)) {
587 puts("Boot from SD0 but without SD0 enabled!\n");
590 debug("mmc0 device found at %p, seq %d\n", dev
, dev
->seq
);
594 env_set("modeboot", "sdboot");
601 if (uclass_get_device_by_name(UCLASS_MMC
,
602 "mmc@ff170000", &dev
) &&
603 uclass_get_device_by_name(UCLASS_MMC
,
604 "sdhci@ff170000", &dev
)) {
605 puts("Boot from SD1 but without SD1 enabled!\n");
608 debug("mmc1 device found at %p, seq %d\n", dev
, dev
->seq
);
612 env_set("modeboot", "sdboot");
617 env_set("modeboot", "nandboot");
621 printf("Invalid Boot Mode:0x%x\n", bootmode
);
626 bootseq_len
= snprintf(NULL
, 0, "%i", bootseq
);
627 debug("Bootseq len: %x\n", bootseq_len
);
631 * One terminating char + one byte for space between mode
632 * and default boot_targets
634 env_targets
= env_get("boot_targets");
636 env_targets_len
= strlen(env_targets
);
638 new_targets
= calloc(1, strlen(mode
) + env_targets_len
+ 2 +
644 sprintf(new_targets
, "%s%x %s", mode
, bootseq
,
645 env_targets
? env_targets
: "");
647 sprintf(new_targets
, "%s %s", mode
,
648 env_targets
? env_targets
: "");
650 env_set("boot_targets", new_targets
);
652 initrd_hi
= gd
->start_addr_sp
- CONFIG_STACK_SIZE
;
653 initrd_hi
= round_down(initrd_hi
, SZ_16M
);
654 env_set_addr("initrd_high", (void *)initrd_hi
);
664 puts("Board: Xilinx ZynqMP\n");