2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
18 #include <dwc3-uboot.h>
23 DECLARE_GLOBAL_DATA_PTR
;
25 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
26 !defined(CONFIG_SPL_BUILD)
27 static xilinx_desc zynqmppl
= XILINX_ZYNQMP_DESC
;
32 } zynqmp_devices
[] = {
80 int chip_id(unsigned char id
)
85 if (current_el() != 3) {
86 regs
.regs
[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID
;
95 * regs[0][31:0] = status of the operation
96 * regs[0][63:32] = CSU.IDCODE register
97 * regs[1][31:0] = CSU.version register
101 regs
.regs
[0] = upper_32_bits(regs
.regs
[0]);
102 regs
.regs
[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK
|
103 ZYNQMP_CSU_IDCODE_SVD_MASK
;
104 regs
.regs
[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT
;
108 regs
.regs
[1] = lower_32_bits(regs
.regs
[1]);
109 regs
.regs
[1] &= ZYNQMP_CSU_SILICON_VER_MASK
;
113 printf("%s, Invalid Req:0x%x\n", __func__
, id
);
118 val
= readl(ZYNQMP_CSU_IDCODE_ADDR
);
119 val
&= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK
|
120 ZYNQMP_CSU_IDCODE_SVD_MASK
;
121 val
>>= ZYNQMP_CSU_IDCODE_SVD_SHIFT
;
124 val
= readl(ZYNQMP_CSU_VER_ADDR
);
125 val
&= ZYNQMP_CSU_SILICON_VER_MASK
;
128 printf("%s, Invalid Req:0x%x\n", __func__
, id
);
135 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
136 !defined(CONFIG_SPL_BUILD)
137 static char *zynqmp_get_silicon_idcode_name(void)
141 id
= chip_id(IDCODE
);
142 for (i
= 0; i
< ARRAY_SIZE(zynqmp_devices
); i
++) {
143 if (zynqmp_devices
[i
].id
== id
)
144 return zynqmp_devices
[i
].name
;
150 int board_early_init_f(void)
152 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
153 zynqmp_pmufw_version();
156 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
163 #define ZYNQMP_VERSION_SIZE 9
167 printf("EL Level:\tEL%d\n", current_el());
169 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
170 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
171 defined(CONFIG_SPL_BUILD))
172 if (current_el() != 3) {
173 static char version
[ZYNQMP_VERSION_SIZE
];
175 strncat(version
, "xczu", 4);
176 zynqmppl
.name
= strncat(version
,
177 zynqmp_get_silicon_idcode_name(),
178 ZYNQMP_VERSION_SIZE
- 5);
179 printf("Chip ID:\t%s\n", zynqmppl
.name
);
181 fpga_add(fpga_xilinx
, &zynqmppl
);
188 int board_early_init_r(void)
192 val
= readl(&crlapb_base
->timestamp_ref_ctrl
);
193 val
&= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT
;
195 if (current_el() == 3 && !val
) {
196 val
= readl(&crlapb_base
->timestamp_ref_ctrl
);
197 val
|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT
;
198 writel(val
, &crlapb_base
->timestamp_ref_ctrl
);
200 /* Program freq register in System counter */
201 writel(zynqmp_get_system_timer_freq(),
202 &iou_scntr_secure
->base_frequency_id_register
);
203 /* And enable system counter */
204 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN
,
205 &iou_scntr_secure
->counter_control_register
);
210 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr
)
212 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
213 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
214 defined(CONFIG_ZYNQ_EEPROM_BUS)
215 i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS
);
217 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR
,
218 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET
,
220 printf("I2C EEPROM MAC address read failed\n");
226 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
227 int dram_init_banksize(void)
229 fdtdec_setup_memory_banksize();
236 if (fdtdec_setup_memory_size() != 0)
244 gd
->ram_size
= CONFIG_SYS_SDRAM_SIZE
;
250 void reset_cpu(ulong addr
)
254 int board_late_init(void)
261 if (!(gd
->flags
& GD_FLG_ENV_DEFAULT
)) {
262 debug("Saved variables - Skipping\n");
266 reg
= readl(&crlapb_base
->boot_mode
);
267 if (reg
>> BOOT_MODE_ALT_SHIFT
)
268 reg
>>= BOOT_MODE_ALT_SHIFT
;
270 bootmode
= reg
& BOOT_MODES_MASK
;
282 case QSPI_MODE_24BIT
:
283 case QSPI_MODE_32BIT
:
300 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
312 printf("Invalid Boot Mode:0x%x\n", bootmode
);
317 * One terminating char + one byte for space between mode
318 * and default boot_targets
320 new_targets
= calloc(1, strlen(mode
) +
321 strlen(env_get("boot_targets")) + 2);
323 sprintf(new_targets
, "%s %s", mode
, env_get("boot_targets"));
324 env_set("boot_targets", new_targets
);
331 puts("Board: Xilinx ZynqMP\n");
335 #ifdef CONFIG_USB_DWC3
336 static struct dwc3_device dwc3_device_data0
= {
337 .maximum_speed
= USB_SPEED_HIGH
,
338 .base
= ZYNQMP_USB0_XHCI_BASEADDR
,
339 .dr_mode
= USB_DR_MODE_PERIPHERAL
,
343 static struct dwc3_device dwc3_device_data1
= {
344 .maximum_speed
= USB_SPEED_HIGH
,
345 .base
= ZYNQMP_USB1_XHCI_BASEADDR
,
346 .dr_mode
= USB_DR_MODE_PERIPHERAL
,
350 int usb_gadget_handle_interrupts(int index
)
352 dwc3_uboot_handle_interrupt(index
);
356 int board_usb_init(int index
, enum usb_init_type init
)
358 debug("%s: index %x\n", __func__
, index
);
360 #if defined(CONFIG_USB_GADGET_DOWNLOAD)
361 g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME
);
366 return dwc3_uboot_init(&dwc3_device_data0
);
368 return dwc3_uboot_init(&dwc3_device_data1
);
374 int board_usb_cleanup(int index
, enum usb_init_type init
)
376 dwc3_uboot_exit(index
);