1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/arch/psu_init_gpl.h>
18 #include <dm/uclass.h>
20 #include <dwc3-uboot.h>
25 DECLARE_GLOBAL_DATA_PTR
;
27 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
28 static struct udevice
*watchdog_dev
;
31 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
32 !defined(CONFIG_SPL_BUILD)
33 static xilinx_desc zynqmppl
= XILINX_ZYNQMP_DESC
;
40 } zynqmp_devices
[] = {
129 { /* For testing purpose only */
173 int chip_id(unsigned char id
)
178 if (current_el() != 3) {
179 regs
.regs
[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID
;
188 * regs[0][31:0] = status of the operation
189 * regs[0][63:32] = CSU.IDCODE register
190 * regs[1][31:0] = CSU.version register
191 * regs[1][63:32] = CSU.IDCODE2 register
195 regs
.regs
[0] = upper_32_bits(regs
.regs
[0]);
196 regs
.regs
[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK
|
197 ZYNQMP_CSU_IDCODE_SVD_MASK
;
198 regs
.regs
[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT
;
202 regs
.regs
[1] = lower_32_bits(regs
.regs
[1]);
203 regs
.regs
[1] &= ZYNQMP_CSU_SILICON_VER_MASK
;
207 regs
.regs
[1] = lower_32_bits(regs
.regs
[1]);
208 regs
.regs
[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT
;
212 printf("%s, Invalid Req:0x%x\n", __func__
, id
);
217 val
= readl(ZYNQMP_CSU_IDCODE_ADDR
);
218 val
&= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK
|
219 ZYNQMP_CSU_IDCODE_SVD_MASK
;
220 val
>>= ZYNQMP_CSU_IDCODE_SVD_SHIFT
;
223 val
= readl(ZYNQMP_CSU_VER_ADDR
);
224 val
&= ZYNQMP_CSU_SILICON_VER_MASK
;
227 printf("%s, Invalid Req:0x%x\n", __func__
, id
);
234 #define ZYNQMP_VERSION_SIZE 9
235 #define ZYNQMP_PL_STATUS_BIT 9
236 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
237 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
239 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
240 !defined(CONFIG_SPL_BUILD)
241 static char *zynqmp_get_silicon_idcode_name(void)
245 static char name
[ZYNQMP_VERSION_SIZE
];
247 id
= chip_id(IDCODE
);
248 ver
= chip_id(IDCODE2
);
250 for (i
= 0; i
< ARRAY_SIZE(zynqmp_devices
); i
++) {
251 if ((zynqmp_devices
[i
].id
== id
) &&
252 (zynqmp_devices
[i
].ver
== (ver
&
253 ZYNQMP_CSU_VERSION_MASK
))) {
254 strncat(name
, "zu", 2);
255 strncat(name
, zynqmp_devices
[i
].name
,
256 ZYNQMP_VERSION_SIZE
- 3);
261 if (i
>= ARRAY_SIZE(zynqmp_devices
))
264 if (!zynqmp_devices
[i
].evexists
)
267 if (ver
& ZYNQMP_PL_STATUS_MASK
)
270 if (strstr(name
, "eg") || strstr(name
, "ev")) {
271 buf
= strstr(name
, "e");
279 int board_early_init_f(void)
282 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
283 zynqmp_pmufw_version();
286 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
290 #if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
291 /* bss is not cleared at time when watchdog_reset() is called */
300 printf("EL Level:\tEL%d\n", current_el());
302 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
303 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
304 defined(CONFIG_SPL_BUILD))
305 if (current_el() != 3) {
306 zynqmppl
.name
= zynqmp_get_silicon_idcode_name();
307 printf("Chip ID:\t%s\n", zynqmppl
.name
);
309 fpga_add(fpga_xilinx
, &zynqmppl
);
313 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
314 if (uclass_get_device(UCLASS_WDT
, 0, &watchdog_dev
)) {
315 puts("Watchdog: Not found!\n");
317 wdt_start(watchdog_dev
, 0, 0);
318 puts("Watchdog: Started\n");
325 #ifdef CONFIG_WATCHDOG
326 /* Called by macro WATCHDOG_RESET */
327 void watchdog_reset(void)
329 # if !defined(CONFIG_SPL_BUILD)
330 static ulong next_reset
;
336 now
= timer_get_us();
338 /* Do not reset the watchdog too often */
339 if (now
> next_reset
) {
340 wdt_reset(watchdog_dev
);
341 next_reset
= now
+ 1000;
347 int board_early_init_r(void)
351 if (current_el() != 3)
354 val
= readl(&crlapb_base
->timestamp_ref_ctrl
);
355 val
&= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT
;
358 val
= readl(&crlapb_base
->timestamp_ref_ctrl
);
359 val
|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT
;
360 writel(val
, &crlapb_base
->timestamp_ref_ctrl
);
362 /* Program freq register in System counter */
363 writel(zynqmp_get_system_timer_freq(),
364 &iou_scntr_secure
->base_frequency_id_register
);
365 /* And enable system counter */
366 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN
,
367 &iou_scntr_secure
->counter_control_register
);
372 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr
)
374 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
375 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
376 defined(CONFIG_ZYNQ_EEPROM_BUS)
377 i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS
);
379 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR
,
380 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET
,
382 printf("I2C EEPROM MAC address read failed\n");
388 unsigned long do_go_exec(ulong (*entry
)(int, char * const []), int argc
,
393 if (current_el() > 1) {
396 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry
,
399 printf("FAIL: current EL is not above EL1\n");
405 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
406 int dram_init_banksize(void)
410 ret
= fdtdec_setup_memory_banksize();
421 if (fdtdec_setup_memory_size() != 0)
427 int dram_init_banksize(void)
429 #if defined(CONFIG_NR_DRAM_BANKS)
430 gd
->bd
->bi_dram
[0].start
= CONFIG_SYS_SDRAM_BASE
;
431 gd
->bd
->bi_dram
[0].size
= get_effective_memsize();
441 gd
->ram_size
= get_ram_size((void *)CONFIG_SYS_SDRAM_BASE
,
442 CONFIG_SYS_SDRAM_SIZE
);
448 void reset_cpu(ulong addr
)
452 int board_late_init(void)
461 if (!(gd
->flags
& GD_FLG_ENV_DEFAULT
)) {
462 debug("Saved variables - Skipping\n");
466 ret
= zynqmp_mmio_read((ulong
)&crlapb_base
->boot_mode
, ®
);
470 if (reg
>> BOOT_MODE_ALT_SHIFT
)
471 reg
>>= BOOT_MODE_ALT_SHIFT
;
473 bootmode
= reg
& BOOT_MODES_MASK
;
480 env_set("modeboot", "usb_dfu_spl");
485 env_set("modeboot", "jtagboot");
487 case QSPI_MODE_24BIT
:
488 case QSPI_MODE_32BIT
:
491 env_set("modeboot", "qspiboot");
496 env_set("modeboot", "emmcboot");
501 env_set("modeboot", "sdboot");
508 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
510 env_set("sdbootdev", "1");
514 env_set("modeboot", "sdboot");
519 env_set("modeboot", "nandboot");
523 printf("Invalid Boot Mode:0x%x\n", bootmode
);
528 * One terminating char + one byte for space between mode
529 * and default boot_targets
531 env_targets
= env_get("boot_targets");
533 new_targets
= calloc(1, strlen(mode
) +
534 strlen(env_targets
) + 2);
535 sprintf(new_targets
, "%s %s", mode
, env_targets
);
537 new_targets
= calloc(1, strlen(mode
) + 2);
538 sprintf(new_targets
, "%s", mode
);
541 env_set("boot_targets", new_targets
);
548 puts("Board: Xilinx ZynqMP\n");
552 #ifdef CONFIG_USB_DWC3
553 static struct dwc3_device dwc3_device_data0
= {
554 .maximum_speed
= USB_SPEED_HIGH
,
555 .base
= ZYNQMP_USB0_XHCI_BASEADDR
,
556 .dr_mode
= USB_DR_MODE_PERIPHERAL
,
560 static struct dwc3_device dwc3_device_data1
= {
561 .maximum_speed
= USB_SPEED_HIGH
,
562 .base
= ZYNQMP_USB1_XHCI_BASEADDR
,
563 .dr_mode
= USB_DR_MODE_PERIPHERAL
,
567 int usb_gadget_handle_interrupts(int index
)
569 dwc3_uboot_handle_interrupt(index
);
573 int board_usb_init(int index
, enum usb_init_type init
)
575 debug("%s: index %x\n", __func__
, index
);
577 #if defined(CONFIG_USB_GADGET_DOWNLOAD)
578 g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME
);
583 return dwc3_uboot_init(&dwc3_device_data0
);
585 return dwc3_uboot_init(&dwc3_device_data1
);
591 int board_usb_cleanup(int index
, enum usb_init_type init
)
593 dwc3_uboot_exit(index
);