2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
18 #include <dwc3-uboot.h>
23 DECLARE_GLOBAL_DATA_PTR
;
25 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
26 !defined(CONFIG_SPL_BUILD)
27 static xilinx_desc zynqmppl
= XILINX_ZYNQMP_DESC
;
32 } zynqmp_devices
[] = {
79 static int chip_id(void)
82 regs
.regs
[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID
;
91 * regs[0][31:0] = status of the operation
92 * regs[0][63:32] = CSU.IDCODE register
93 * regs[1][31:0] = CSU.version register
95 regs
.regs
[0] = upper_32_bits(regs
.regs
[0]);
96 regs
.regs
[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK
|
97 ZYNQMP_CSU_IDCODE_SVD_MASK
;
98 regs
.regs
[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT
;
103 static char *zynqmp_get_silicon_idcode_name(void)
108 for (i
= 0; i
< ARRAY_SIZE(zynqmp_devices
); i
++) {
109 if (zynqmp_devices
[i
].id
== id
)
110 return zynqmp_devices
[i
].name
;
116 #define ZYNQMP_VERSION_SIZE 9
120 printf("EL Level:\tEL%d\n", current_el());
122 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
123 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
124 defined(CONFIG_SPL_BUILD))
125 if (current_el() != 3) {
126 static char version
[ZYNQMP_VERSION_SIZE
];
128 strncat(version
, "xczu", ZYNQMP_VERSION_SIZE
);
129 zynqmppl
.name
= strncat(version
,
130 zynqmp_get_silicon_idcode_name(),
131 ZYNQMP_VERSION_SIZE
);
132 printf("Chip ID:\t%s\n", zynqmppl
.name
);
134 fpga_add(fpga_xilinx
, &zynqmppl
);
141 int board_early_init_r(void)
145 if (current_el() == 3) {
146 val
= readl(&crlapb_base
->timestamp_ref_ctrl
);
147 val
|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT
;
148 writel(val
, &crlapb_base
->timestamp_ref_ctrl
);
150 /* Program freq register in System counter */
151 writel(zynqmp_get_system_timer_freq(),
152 &iou_scntr_secure
->base_frequency_id_register
);
153 /* And enable system counter */
154 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN
,
155 &iou_scntr_secure
->counter_control_register
);
157 /* Program freq register in System counter and enable system counter */
158 writel(gd
->cpu_clk
, &iou_scntr
->base_frequency_id_register
);
159 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG
|
160 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN
,
161 &iou_scntr
->counter_control_register
);
166 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr
)
168 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
169 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
170 defined(CONFIG_ZYNQ_EEPROM_BUS)
171 i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS
);
173 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR
,
174 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET
,
176 printf("I2C EEPROM MAC address read failed\n");
182 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
184 * fdt_get_reg - Fill buffer by information from DT
186 static phys_size_t
fdt_get_reg(const void *fdt
, int nodeoffset
, void *buf
,
187 const u32
*cell
, int n
)
190 int parent_offset
= fdt_parent_offset(fdt
, nodeoffset
);
191 int address_cells
= fdt_address_cells(fdt
, parent_offset
);
192 int size_cells
= fdt_size_cells(fdt
, parent_offset
);
197 debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
198 __func__
, address_cells
, size_cells
, buf
, cell
);
200 /* Check memory bank setup */
201 banks
= n
% (address_cells
+ size_cells
);
203 panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
204 n
, address_cells
, size_cells
);
206 banks
= n
/ (address_cells
+ size_cells
);
208 for (b
= 0; b
< banks
; b
++) {
209 debug("%s: Bank #%d:\n", __func__
, b
);
210 if (address_cells
== 2) {
214 val
= fdt64_to_cpu(val
);
215 debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
216 __func__
, val
, p
, &cell
[i
]);
217 *(phys_addr_t
*)p
= val
;
219 debug("%s: addr32=%x, ptr=%p\n",
220 __func__
, fdt32_to_cpu(cell
[i
]), p
);
221 *(phys_addr_t
*)p
= fdt32_to_cpu(cell
[i
]);
223 p
+= sizeof(phys_addr_t
);
226 debug("%s: pa=%p, i=%x, size=%zu\n", __func__
, p
, i
,
227 sizeof(phys_addr_t
));
229 if (size_cells
== 2) {
233 vals
= fdt64_to_cpu(vals
);
235 debug("%s: size64=%llx, ptr=%p, cell=%p\n",
236 __func__
, vals
, p
, &cell
[i
]);
237 *(phys_size_t
*)p
= vals
;
239 debug("%s: size32=%x, ptr=%p\n",
240 __func__
, fdt32_to_cpu(cell
[i
]), p
);
241 *(phys_size_t
*)p
= fdt32_to_cpu(cell
[i
]);
243 p
+= sizeof(phys_size_t
);
246 debug("%s: ps=%p, i=%x, size=%zu\n",
247 __func__
, p
, i
, sizeof(phys_size_t
));
250 /* Return the first address size */
251 return *(phys_size_t
*)((char *)buf
+ sizeof(phys_addr_t
));
254 #define FDT_REG_SIZE sizeof(u32)
255 /* Temp location for sharing data for storing */
256 /* Up to 64-bit address + 64-bit size */
257 static u8 tmp
[CONFIG_NR_DRAM_BANKS
* 16];
259 void dram_init_banksize(void)
263 memcpy(&gd
->bd
->bi_dram
[0], &tmp
, sizeof(tmp
));
265 for (bank
= 0; bank
< CONFIG_NR_DRAM_BANKS
; bank
++) {
266 debug("Bank #%d: start %llx\n", bank
,
267 (unsigned long long)gd
->bd
->bi_dram
[bank
].start
);
268 debug("Bank #%d: size %llx\n", bank
,
269 (unsigned long long)gd
->bd
->bi_dram
[bank
].size
);
276 const void *blob
= gd
->fdt_blob
;
279 memset(&tmp
, 0, sizeof(tmp
));
281 /* find or create "/memory" node. */
282 node
= fdt_subnode_offset(blob
, 0, "memory");
284 printf("%s: Can't get memory node\n", __func__
);
288 /* Get pointer to cells and lenght of it */
289 cell
= fdt_getprop(blob
, node
, "reg", &len
);
291 printf("%s: Can't get reg property\n", __func__
);
295 gd
->ram_size
= fdt_get_reg(blob
, node
, &tmp
, cell
, len
/ FDT_REG_SIZE
);
297 debug("%s: Initial DRAM size %llx\n", __func__
, (u64
)gd
->ram_size
);
304 gd
->ram_size
= CONFIG_SYS_SDRAM_SIZE
;
310 void reset_cpu(ulong addr
)
314 #ifdef CONFIG_SCSI_AHCI_PLAT
317 #if defined(CONFIG_SATA_CEVA)
320 ahci_init((void __iomem
*)ZYNQMP_SATA_BASEADDR
);
325 int board_late_init(void)
332 if (!(gd
->flags
& GD_FLG_ENV_DEFAULT
)) {
333 debug("Saved variables - Skipping\n");
337 reg
= readl(&crlapb_base
->boot_mode
);
338 if (reg
>> BOOT_MODE_ALT_SHIFT
)
339 reg
>>= BOOT_MODE_ALT_SHIFT
;
341 bootmode
= reg
& BOOT_MODES_MASK
;
353 case QSPI_MODE_24BIT
:
354 case QSPI_MODE_32BIT
:
371 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
383 printf("Invalid Boot Mode:0x%x\n", bootmode
);
388 * One terminating char + one byte for space between mode
389 * and default boot_targets
391 new_targets
= calloc(1, strlen(mode
) +
392 strlen(getenv("boot_targets")) + 2);
394 sprintf(new_targets
, "%s %s", mode
, getenv("boot_targets"));
395 setenv("boot_targets", new_targets
);
402 puts("Board: Xilinx ZynqMP\n");
406 #ifdef CONFIG_USB_DWC3
407 static struct dwc3_device dwc3_device_data0
= {
408 .maximum_speed
= USB_SPEED_HIGH
,
409 .base
= ZYNQMP_USB0_XHCI_BASEADDR
,
410 .dr_mode
= USB_DR_MODE_PERIPHERAL
,
414 static struct dwc3_device dwc3_device_data1
= {
415 .maximum_speed
= USB_SPEED_HIGH
,
416 .base
= ZYNQMP_USB1_XHCI_BASEADDR
,
417 .dr_mode
= USB_DR_MODE_PERIPHERAL
,
421 int usb_gadget_handle_interrupts(int index
)
423 dwc3_uboot_handle_interrupt(index
);
427 int board_usb_init(int index
, enum usb_init_type init
)
429 debug("%s: index %x\n", __func__
, index
);
431 #if defined(CONFIG_USB_GADGET_DOWNLOAD)
432 g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME
);
437 return dwc3_uboot_init(&dwc3_device_data0
);
439 return dwc3_uboot_init(&dwc3_device_data1
);
445 int board_usb_cleanup(int index
, enum usb_init_type init
)
447 dwc3_uboot_exit(index
);