2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
18 #include <dwc3-uboot.h>
21 DECLARE_GLOBAL_DATA_PTR
;
25 printf("EL Level:\tEL%d\n", current_el());
30 int board_early_init_r(void)
34 if (current_el() == 3) {
35 val
= readl(&crlapb_base
->timestamp_ref_ctrl
);
36 val
|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT
;
37 writel(val
, &crlapb_base
->timestamp_ref_ctrl
);
39 /* Program freq register in System counter */
40 writel(zynqmp_get_system_timer_freq(),
41 &iou_scntr_secure
->base_frequency_id_register
);
42 /* And enable system counter */
43 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN
,
44 &iou_scntr_secure
->counter_control_register
);
46 /* Program freq register in System counter and enable system counter */
47 writel(gd
->cpu_clk
, &iou_scntr
->base_frequency_id_register
);
48 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG
|
49 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN
,
50 &iou_scntr
->counter_control_register
);
55 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr
)
57 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
58 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
59 defined(CONFIG_ZYNQ_EEPROM_BUS)
60 i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS
);
62 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR
,
63 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET
,
65 printf("I2C EEPROM MAC address read failed\n");
71 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
73 * fdt_get_reg - Fill buffer by information from DT
75 static phys_size_t
fdt_get_reg(const void *fdt
, int nodeoffset
, void *buf
,
76 const u32
*cell
, int n
)
79 int parent_offset
= fdt_parent_offset(fdt
, nodeoffset
);
80 int address_cells
= fdt_address_cells(fdt
, parent_offset
);
81 int size_cells
= fdt_size_cells(fdt
, parent_offset
);
86 debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
87 __func__
, address_cells
, size_cells
, buf
, cell
);
89 /* Check memory bank setup */
90 banks
= n
% (address_cells
+ size_cells
);
92 panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
93 n
, address_cells
, size_cells
);
95 banks
= n
/ (address_cells
+ size_cells
);
97 for (b
= 0; b
< banks
; b
++) {
98 debug("%s: Bank #%d:\n", __func__
, b
);
99 if (address_cells
== 2) {
103 val
= fdt64_to_cpu(val
);
104 debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
105 __func__
, val
, p
, &cell
[i
]);
106 *(phys_addr_t
*)p
= val
;
108 debug("%s: addr32=%x, ptr=%p\n",
109 __func__
, fdt32_to_cpu(cell
[i
]), p
);
110 *(phys_addr_t
*)p
= fdt32_to_cpu(cell
[i
]);
112 p
+= sizeof(phys_addr_t
);
115 debug("%s: pa=%p, i=%x, size=%zu\n", __func__
, p
, i
,
116 sizeof(phys_addr_t
));
118 if (size_cells
== 2) {
122 vals
= fdt64_to_cpu(vals
);
124 debug("%s: size64=%llx, ptr=%p, cell=%p\n",
125 __func__
, vals
, p
, &cell
[i
]);
126 *(phys_size_t
*)p
= vals
;
128 debug("%s: size32=%x, ptr=%p\n",
129 __func__
, fdt32_to_cpu(cell
[i
]), p
);
130 *(phys_size_t
*)p
= fdt32_to_cpu(cell
[i
]);
132 p
+= sizeof(phys_size_t
);
135 debug("%s: ps=%p, i=%x, size=%zu\n",
136 __func__
, p
, i
, sizeof(phys_size_t
));
139 /* Return the first address size */
140 return *(phys_size_t
*)((char *)buf
+ sizeof(phys_addr_t
));
143 #define FDT_REG_SIZE sizeof(u32)
144 /* Temp location for sharing data for storing */
145 /* Up to 64-bit address + 64-bit size */
146 static u8 tmp
[CONFIG_NR_DRAM_BANKS
* 16];
148 void dram_init_banksize(void)
152 memcpy(&gd
->bd
->bi_dram
[0], &tmp
, sizeof(tmp
));
154 for (bank
= 0; bank
< CONFIG_NR_DRAM_BANKS
; bank
++) {
155 debug("Bank #%d: start %llx\n", bank
,
156 (unsigned long long)gd
->bd
->bi_dram
[bank
].start
);
157 debug("Bank #%d: size %llx\n", bank
,
158 (unsigned long long)gd
->bd
->bi_dram
[bank
].size
);
165 const void *blob
= gd
->fdt_blob
;
168 memset(&tmp
, 0, sizeof(tmp
));
170 /* find or create "/memory" node. */
171 node
= fdt_subnode_offset(blob
, 0, "memory");
173 printf("%s: Can't get memory node\n", __func__
);
177 /* Get pointer to cells and lenght of it */
178 cell
= fdt_getprop(blob
, node
, "reg", &len
);
180 printf("%s: Can't get reg property\n", __func__
);
184 gd
->ram_size
= fdt_get_reg(blob
, node
, &tmp
, cell
, len
/ FDT_REG_SIZE
);
186 debug("%s: Initial DRAM size %llx\n", __func__
, (u64
)gd
->ram_size
);
193 gd
->ram_size
= CONFIG_SYS_SDRAM_SIZE
;
199 void reset_cpu(ulong addr
)
203 #ifdef CONFIG_SCSI_AHCI_PLAT
206 #if defined(CONFIG_SATA_CEVA)
209 ahci_init((void __iomem
*)ZYNQMP_SATA_BASEADDR
);
214 int board_late_init(void)
221 if (!(gd
->flags
& GD_FLG_ENV_DEFAULT
)) {
222 debug("Saved variables - Skipping\n");
226 reg
= readl(&crlapb_base
->boot_mode
);
227 bootmode
= reg
& BOOT_MODES_MASK
;
235 case QSPI_MODE_24BIT
:
236 case QSPI_MODE_32BIT
:
250 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
262 printf("Invalid Boot Mode:0x%x\n", bootmode
);
267 * One terminating char + one byte for space between mode
268 * and default boot_targets
270 new_targets
= calloc(1, strlen(mode
) +
271 strlen(getenv("boot_targets")) + 2);
273 sprintf(new_targets
, "%s %s", mode
, getenv("boot_targets"));
274 setenv("boot_targets", new_targets
);
281 puts("Board: Xilinx ZynqMP\n");
285 #ifdef CONFIG_USB_DWC3
286 static struct dwc3_device dwc3_device_data
= {
287 .maximum_speed
= USB_SPEED_HIGH
,
288 .base
= ZYNQMP_USB0_XHCI_BASEADDR
,
289 .dr_mode
= USB_DR_MODE_PERIPHERAL
,
293 int usb_gadget_handle_interrupts(void)
295 dwc3_uboot_handle_interrupt(0);
299 int board_usb_init(int index
, enum usb_init_type init
)
301 return dwc3_uboot_init(&dwc3_device_data
);
304 int board_usb_cleanup(int index
, enum usb_init_type init
)
306 dwc3_uboot_exit(index
);
311 void reset_misc(void)
313 psci_system_reset(true);