2 * (C) Copyright 2006 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #if defined(CONFIG_CMD_NAND)
26 #ifdef CONFIG_NEW_NAND_CODE
29 #include <asm/arch/pxa-regs.h>
32 # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
34 # define DFC_DEBUG1(fmt, args...)
38 # define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
40 # define DFC_DEBUG2(fmt, args...)
44 # define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
46 # define DFC_DEBUG3(fmt, args...)
49 #define MIN(x, y) ((x < y) ? x : y)
51 /* These really don't belong here, as they are specific to the NAND Model */
52 static uint8_t scan_ff_pattern
[] = { 0xff, 0xff };
54 static struct nand_bbt_descr delta_bbt_descr
= {
58 .pattern
= scan_ff_pattern
61 static struct nand_ecclayout delta_oob
= {
63 .eccpos
= {2, 3, 4, 5, 6, 7},
64 .oobfree
= { {8, 2}, {12, 4} }
68 * not required for Monahans DFC
70 static void dfc_hwcontrol(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
76 /* read device ready pin */
77 static int dfc_device_ready(struct mtd_info
*mtdinfo
)
88 * Write buf to the DFC Controller Data Buffer
90 static void dfc_write_buf(struct mtd_info
*mtd
, const u_char
*buf
, int len
)
92 unsigned long bytes_multi
= len
& 0xfffffffc;
93 unsigned long rest
= len
& 0x3;
94 unsigned long *long_buf
;
97 DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len
, *((unsigned long*) buf
));
99 for(i
=0; i
<bytes_multi
; i
+=4) {
100 long_buf
= (unsigned long*) &buf
[i
];
105 printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
112 * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
114 * Shouldn't this be "u_char * const buf" ?
116 static void dfc_read_buf(struct mtd_info
*mtd
, u_char
* const buf
, int len
)
120 /* we have to be carefull not to overflow the buffer if len is
121 * not a multiple of 4 */
122 unsigned long bytes_multi
= len
& 0xfffffffc;
123 unsigned long rest
= len
& 0x3;
124 unsigned long *long_buf
;
126 DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len
);
127 /* if there are any, first copy multiple of 4 bytes */
129 for(i
=0; i
<bytes_multi
; i
+=4) {
130 long_buf
= (unsigned long*) &buf
[i
];
135 /* ...then the rest */
137 unsigned long rest_data
= NDDB
;
139 buf
[i
+j
] = (u_char
) ((rest_data
>>j
) & 0xff);
146 * read a word. Not implemented as not used in NAND code.
148 static u16
dfc_read_word(struct mtd_info
*mtd
)
150 printf("dfc_read_word: UNIMPLEMENTED.\n");
154 /* global var, too bad: mk@tbd: move to ->priv pointer */
155 static unsigned long read_buf
= 0;
156 static int bytes_read
= -1;
159 * read a byte from NDDB Because we can only read 4 bytes from NDDB at
160 * a time, we buffer the remaining bytes. The buffer is reset when a
161 * new command is sent to the chip.
164 * This function is currently only used to read status and id
165 * bytes. For these commands always 8 bytes need to be read from
166 * NDDB. So we read and discard these bytes right now. In case this
167 * function is used for anything else in the future, we must check
168 * what was the last command issued and read the appropriate amount of
169 * bytes respectively.
171 static u_char
dfc_read_byte(struct mtd_info
*mtd
)
181 byte
= (unsigned char) (read_buf
>>(8 * bytes_read
++));
185 DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read
- 1, byte
, read_buf
);
189 /* calculate delta between OSCR values start and now */
190 static unsigned long get_delta(unsigned long start
)
192 unsigned long cur
= OSCR
;
194 if(cur
< start
) /* OSCR overflowed */
195 return (cur
+ (start
^0xffffffff));
197 return (cur
- start
);
200 /* delay function, this doesn't belong here */
201 static void wait_us(unsigned long us
)
203 unsigned long start
= OSCR
;
206 while (get_delta(start
) < us
) {
211 static void dfc_clear_nddb(void)
213 NDCR
&= ~NDCR_ND_RUN
;
214 wait_us(CFG_NAND_OTHER_TO
);
217 /* wait_event with timeout */
218 static unsigned long dfc_wait_event(unsigned long event
)
220 unsigned long ndsr
, timeout
, start
= OSCR
;
224 else if(event
& (NDSR_CS0_CMDD
| NDSR_CS0_BBD
))
225 timeout
= CFG_NAND_PROG_ERASE_TO
* OSCR_CLK_FREQ
;
227 timeout
= CFG_NAND_OTHER_TO
* OSCR_CLK_FREQ
;
235 if(get_delta(start
) > timeout
) {
236 DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event
);
244 /* we don't always wan't to do this */
245 static void dfc_new_cmd(void)
248 unsigned long status
;
250 while(retry
++ <= CFG_NAND_SENDCMD_RETRY
) {
254 /* set NDCR[NDRUN] */
255 if(!(NDCR
& NDCR_ND_RUN
))
258 status
= dfc_wait_event(NDSR_WRCMDREQ
);
260 if(status
& NDSR_WRCMDREQ
)
263 DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry
);
266 DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry
);
269 /* this function is called after Programm and Erase Operations to
270 * check for success or failure */
271 static int dfc_wait(struct mtd_info
*mtd
, struct nand_chip
*this)
273 unsigned long ndsr
=0, event
=0;
274 int state
= this->state
;
276 if(state
== FL_WRITING
) {
277 event
= NDSR_CS0_CMDD
| NDSR_CS0_BBD
;
278 } else if(state
== FL_ERASING
) {
279 event
= NDSR_CS0_CMDD
| NDSR_CS0_BBD
;
282 ndsr
= dfc_wait_event(event
);
284 if((ndsr
& NDSR_CS0_BBD
) || (ndsr
& 0xff000000))
285 return(0x1); /* Status Read error */
289 /* cmdfunc send commands to the DFC */
290 static void dfc_cmdfunc(struct mtd_info
*mtd
, unsigned command
,
291 int column
, int page_addr
)
293 /* register struct nand_chip *this = mtd->priv; */
294 unsigned long ndcb0
=0, ndcb1
=0, ndcb2
=0, event
=0;
296 /* clear the ugly byte read buffer */
302 DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr
, (column
>>1));
304 ndcb0
= (NAND_CMD_READ0
| (4<<16));
305 column
>>= 1; /* adjust for 16 bit bus */
306 ndcb1
= (((column
>>1) & 0xff) |
307 ((page_addr
<<8) & 0xff00) |
308 ((page_addr
<<8) & 0xff0000) |
309 ((page_addr
<<8) & 0xff000000)); /* make this 0x01000000 ? */
313 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
315 case NAND_CMD_READOOB
:
316 DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
318 case NAND_CMD_READID
:
320 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
321 ndcb0
= (NAND_CMD_READID
| (3 << 21) | (1 << 16)); /* addr cycles*/
324 case NAND_CMD_PAGEPROG
:
325 /* sent as a multicommand in NAND_CMD_SEQIN */
326 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
328 case NAND_CMD_ERASE1
:
329 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr
, (column
>>1));
331 ndcb0
= (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
332 ndcb1
= (page_addr
& 0x00ffffff);
334 case NAND_CMD_ERASE2
:
335 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
338 /* send PAGE_PROG command(0x1080) */
340 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr
, (column
>>1));
341 ndcb0
= (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
342 column
>>= 1; /* adjust for 16 bit bus */
343 ndcb1
= (((column
>>1) & 0xff) |
344 ((page_addr
<<8) & 0xff00) |
345 ((page_addr
<<8) & 0xff0000) |
346 ((page_addr
<<8) & 0xff000000)); /* make this 0x01000000 ? */
349 case NAND_CMD_STATUS
:
350 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
352 ndcb0
= NAND_CMD_STATUS
| (4<<21);
356 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
357 ndcb0
= NAND_CMD_RESET
| (5<<21);
358 event
= NDSR_CS0_CMDD
;
361 printk("dfc_cmdfunc: error, unsupported command.\n");
371 dfc_wait_event(event
);
376 static void dfc_gpio_init(void)
378 DFC_DEBUG2("Setting up DFC GPIO's.\n");
380 /* no idea what is done here, see zylonite.c */
383 DF_ALE_WE1
= 0x00000001;
384 DF_ALE_WE2
= 0x00000001;
385 DF_nCS0
= 0x00000001;
386 DF_nCS1
= 0x00000001;
394 DF_IO10
= 0x00000001;
396 DF_IO11
= 0x00000001;
398 DF_IO12
= 0x00000001;
400 DF_IO13
= 0x00000001;
402 DF_IO14
= 0x00000001;
404 DF_IO15
= 0x00000001;
414 * Board-specific NAND initialization. The following members of the
415 * argument are board-specific (per include/linux/mtd/nand_new.h):
416 * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
417 * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
418 * - cmd_ctrl: hardwarespecific function for accesing control-lines
419 * - dev_ready: hardwarespecific function for accesing device ready/busy line
420 * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
421 * only be provided if a hardware ECC is available
422 * - ecc.mode: mode of ecc, see defines
423 * - chip_delay: chip dependent delay for transfering data from array to
425 * - options: various chip options. They can partly be set to inform
426 * nand_scan about special functionality. See the defines for further
428 * Members with a "?" were not set in the merged testing-NAND branch,
429 * so they are not set here either.
431 int board_nand_init(struct nand_chip
*nand
)
433 unsigned long tCH
, tCS
, tWH
, tWP
, tRH
, tRP
, tRP_high
, tR
, tWHR
, tAR
;
435 /* set up GPIO Control Registers */
438 /* turn on the NAND Controller Clock (104 MHz @ D0) */
439 CKENA
|= (CKENA_4_NAND
| CKENA_9_SMC
);
441 #undef CFG_TIMING_TIGHT
442 #ifndef CFG_TIMING_TIGHT
443 tCH
= MIN(((unsigned long) (NAND_TIMING_tCH
* DFC_CLK_PER_US
) + 1),
445 tCS
= MIN(((unsigned long) (NAND_TIMING_tCS
* DFC_CLK_PER_US
) + 1),
447 tWH
= MIN(((unsigned long) (NAND_TIMING_tWH
* DFC_CLK_PER_US
) + 1),
449 tWP
= MIN(((unsigned long) (NAND_TIMING_tWP
* DFC_CLK_PER_US
) + 1),
451 tRH
= MIN(((unsigned long) (NAND_TIMING_tRH
* DFC_CLK_PER_US
) + 1),
453 tRP
= MIN(((unsigned long) (NAND_TIMING_tRP
* DFC_CLK_PER_US
) + 1),
455 tR
= MIN(((unsigned long) (NAND_TIMING_tR
* DFC_CLK_PER_US
) + 1),
457 tWHR
= MIN(((unsigned long) (NAND_TIMING_tWHR
* DFC_CLK_PER_US
) + 1),
459 tAR
= MIN(((unsigned long) (NAND_TIMING_tAR
* DFC_CLK_PER_US
) + 1),
461 #else /* this is the tight timing */
463 tCH
= MIN(((unsigned long) (NAND_TIMING_tCH
* DFC_CLK_PER_US
)),
465 tCS
= MIN(((unsigned long) (NAND_TIMING_tCS
* DFC_CLK_PER_US
)),
467 tWH
= MIN(((unsigned long) (NAND_TIMING_tWH
* DFC_CLK_PER_US
)),
469 tWP
= MIN(((unsigned long) (NAND_TIMING_tWP
* DFC_CLK_PER_US
)),
471 tRH
= MIN(((unsigned long) (NAND_TIMING_tRH
* DFC_CLK_PER_US
)),
473 tRP
= MIN(((unsigned long) (NAND_TIMING_tRP
* DFC_CLK_PER_US
)),
475 tR
= MIN(((unsigned long) (NAND_TIMING_tR
* DFC_CLK_PER_US
) - tCH
- 2),
477 tWHR
= MIN(((unsigned long) (NAND_TIMING_tWHR
* DFC_CLK_PER_US
) - tCH
- 2),
479 tAR
= MIN(((unsigned long) (NAND_TIMING_tAR
* DFC_CLK_PER_US
) - 2),
481 #endif /* CFG_TIMING_TIGHT */
484 DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH
, tCS
, tWH
, tWP
, tRH
, tRP
, tR
, tWHR
, tAR
);
486 /* tRP value is split in the register */
494 NDTR0CS0
= (tCH
<< 19) |
502 NDTR1CS0
= (tR
<< 16) |
506 /* If it doesn't work (unlikely) think about:
508 * - chip select don't care
509 * - read id byte count
511 * Intentionally enabled by not setting bits:
514 * - cs don't care, see if we can enable later!
515 * - row address start position (after second cycle)
516 * - pages per block = 32
517 * - ND_RDY : clears command buffer
519 /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
521 NDCR
= (NDCR_SPARE_EN
| /* use the spare area */
522 NDCR_DWIDTH_C
| /* 16bit DFC data bus width */
523 NDCR_DWIDTH_M
| /* 16 bit Flash device data bus width */
524 (2 << 16) | /* read id count = 7 ???? mk@tbd */
525 NDCR_ND_ARB_EN
| /* enable bus arbiter */
526 NDCR_RDYM
| /* flash device ready ir masked */
527 NDCR_CS0_PAGEDM
| /* ND_nCSx page done ir masked */
529 NDCR_CS0_CMDDM
| /* ND_CSx command done ir masked */
531 NDCR_CS0_BBDM
| /* ND_CSx bad block detect ir masked */
533 NDCR_DBERRM
| /* double bit error ir masked */
534 NDCR_SBERRM
| /* single bit error ir masked */
535 NDCR_WRDREQM
| /* write data request ir masked */
536 NDCR_RDDREQM
| /* read data request ir masked */
537 NDCR_WRCMDREQM
); /* write command request ir masked */
540 /* wait 10 us due to cmd buffer clear reset */
543 nand
->cmd_ctrl
= dfc_hwcontrol
;
544 /* nand->dev_ready = dfc_device_ready; */
545 nand
->ecc
.mode
= NAND_ECC_SOFT
;
546 nand
->ecc
.layout
= &delta_oob
;
547 nand
->options
= NAND_BUSWIDTH_16
;
548 nand
->waitfunc
= dfc_wait
;
549 nand
->read_byte
= dfc_read_byte
;
550 nand
->read_word
= dfc_read_word
;
551 nand
->read_buf
= dfc_read_buf
;
552 nand
->write_buf
= dfc_write_buf
;
554 nand
->cmdfunc
= dfc_cmdfunc
;
555 nand
->badblock_pattern
= &delta_bbt_descr
;
560 #error "U-Boot legacy NAND support not available for Monahans DFC."