board/zylonite/nand.c

   1 /*
   2  * (C) Copyright 2006 DENX Software Engineering
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24
  25 #if defined(CONFIG_CMD_NAND)
  26 #ifdef CONFIG_NEW_NAND_CODE
  27
  28 #include <nand.h>
  29 #include <asm/arch/pxa-regs.h>
  30
  31 #ifdef CFG_DFC_DEBUG1
  32 # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
  33 #else
  34 # define DFC_DEBUG1(fmt, args...)
  35 #endif
  36
  37 #ifdef CFG_DFC_DEBUG2
  38 # define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
  39 #else
  40 # define DFC_DEBUG2(fmt, args...)
  41 #endif
  42
  43 #ifdef CFG_DFC_DEBUG3
  44 # define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
  45 #else
  46 # define DFC_DEBUG3(fmt, args...)
  47 #endif
  48
  49 #define MIN(x, y)               ((x < y) ? x : y)
  50
  51 /* These really don't belong here, as they are specific to the NAND Model */
  52 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
  53
  54 static struct nand_bbt_descr delta_bbt_descr = {
  55         .options = 0,
  56         .offs = 0,
  57         .len = 2,
  58         .pattern = scan_ff_pattern
  59 };
  60
  61 static struct nand_oobinfo delta_oob = {
  62         .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
  63         .eccbytes = 6,
  64         .eccpos = {2, 3, 4, 5, 6, 7},
  65         .oobfree = { {8, 2}, {12, 4} }
  66 };
  67
  68
  69 /*
  70  * not required for Monahans DFC
  71  */
  72 static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  73 {
  74         return;
  75 }
  76
  77 #if 0
  78 /* read device ready pin */
  79 static int dfc_device_ready(struct mtd_info *mtdinfo)
  80 {
  81         if(NDSR & NDSR_RDY)
  82                 return 1;
  83         else
  84                 return 0;
  85         return 0;
  86 }
  87 #endif
  88
  89 /*
  90  * Write buf to the DFC Controller Data Buffer
  91  */
  92 static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
  93 {
  94         unsigned long bytes_multi = len & 0xfffffffc;
  95         unsigned long rest = len & 0x3;
  96         unsigned long *long_buf;
  97         int i;
  98
  99         DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
 100         if(bytes_multi) {
 101                 for(i=0; i<bytes_multi; i+=4) {
 102                         long_buf = (unsigned long*) &buf[i];
 103                         NDDB = *long_buf;
 104                 }
 105         }
 106         if(rest) {
 107                 printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
 108         }
 109         return;
 110 }
 111
 112
 113 /* The original:
 114  * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
 115  *
 116  * Shouldn't this be "u_char * const buf" ?
 117  */
 118 static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
 119 {
 120         int i=0, j;
 121
 122         /* we have to be carefull not to overflow the buffer if len is
 123          * not a multiple of 4 */
 124         unsigned long bytes_multi = len & 0xfffffffc;
 125         unsigned long rest = len & 0x3;
 126         unsigned long *long_buf;
 127
 128         DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
 129         /* if there are any, first copy multiple of 4 bytes */
 130         if(bytes_multi) {
 131                 for(i=0; i<bytes_multi; i+=4) {
 132                         long_buf = (unsigned long*) &buf[i];
 133                         *long_buf = NDDB;
 134                 }
 135         }
 136
 137         /* ...then the rest */
 138         if(rest) {
 139                 unsigned long rest_data = NDDB;
 140                 for(j=0;j<rest; j++)
 141                         buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
 142         }
 143
 144         return;
 145 }
 146
 147 /*
 148  * read a word. Not implemented as not used in NAND code.
 149  */
 150 static u16 dfc_read_word(struct mtd_info *mtd)
 151 {
 152         printf("dfc_read_word: UNIMPLEMENTED.\n");
 153         return 0;
 154 }
 155
 156 /* global var, too bad: mk@tbd: move to ->priv pointer */
 157 static unsigned long read_buf = 0;
 158 static int bytes_read = -1;
 159
 160 /*
 161  * read a byte from NDDB Because we can only read 4 bytes from NDDB at
 162  * a time, we buffer the remaining bytes. The buffer is reset when a
 163  * new command is sent to the chip.
 164  *
 165  * WARNING:
 166  * This function is currently only used to read status and id
 167  * bytes. For these commands always 8 bytes need to be read from
 168  * NDDB. So we read and discard these bytes right now. In case this
 169  * function is used for anything else in the future, we must check
 170  * what was the last command issued and read the appropriate amount of
 171  * bytes respectively.
 172  */
 173 static u_char dfc_read_byte(struct mtd_info *mtd)
 174 {
 175         unsigned char byte;
 176         unsigned long dummy;
 177
 178         if(bytes_read < 0) {
 179                 read_buf = NDDB;
 180                 dummy = NDDB;
 181                 bytes_read = 0;
 182         }
 183         byte = (unsigned char) (read_buf>>(8 * bytes_read++));
 184         if(bytes_read >= 4)
 185                 bytes_read = -1;
 186
 187         DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
 188         return byte;
 189 }
 190
 191 /* calculate delta between OSCR values start and now  */
 192 static unsigned long get_delta(unsigned long start)
 193 {
 194         unsigned long cur = OSCR;
 195
 196         if(cur < start) /* OSCR overflowed */
 197                 return (cur + (start^0xffffffff));
 198         else
 199                 return (cur - start);
 200 }
 201
 202 /* delay function, this doesn't belong here */
 203 static void wait_us(unsigned long us)
 204 {
 205         unsigned long start = OSCR;
 206         us *= OSCR_CLK_FREQ;
 207
 208         while (get_delta(start) < us) {
 209                 /* do nothing */
 210         }
 211 }
 212
 213 static void dfc_clear_nddb(void)
 214 {
 215         NDCR &= ~NDCR_ND_RUN;
 216         wait_us(CFG_NAND_OTHER_TO);
 217 }
 218
 219 /* wait_event with timeout */
 220 static unsigned long dfc_wait_event(unsigned long event)
 221 {
 222         unsigned long ndsr, timeout, start = OSCR;
 223
 224         if(!event)
 225                 return 0xff000000;
 226         else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
 227                 timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
 228         else
 229                 timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ;
 230
 231         while(1) {
 232                 ndsr = NDSR;
 233                 if(ndsr & event) {
 234                         NDSR |= event;
 235                         break;
 236                 }
 237                 if(get_delta(start) > timeout) {
 238                         DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
 239                         return 0xff000000;
 240                 }
 241
 242         }
 243         return ndsr;
 244 }
 245
 246 /* we don't always wan't to do this */
 247 static void dfc_new_cmd(void)
 248 {
 249         int retry = 0;
 250         unsigned long status;
 251
 252         while(retry++ <= CFG_NAND_SENDCMD_RETRY) {
 253                 /* Clear NDSR */
 254                 NDSR = 0xFFF;
 255
 256                 /* set NDCR[NDRUN] */
 257                 if(!(NDCR & NDCR_ND_RUN))
 258                         NDCR |= NDCR_ND_RUN;
 259
 260                 status = dfc_wait_event(NDSR_WRCMDREQ);
 261
 262                 if(status & NDSR_WRCMDREQ)
 263                         return;
 264
 265                 DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
 266                 dfc_clear_nddb();
 267         }
 268         DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
 269 }
 270
 271 /* this function is called after Programm and Erase Operations to
 272  * check for success or failure */
 273 static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
 274 {
 275         unsigned long ndsr=0, event=0;
 276         int state = this->state;
 277
 278         if(state == FL_WRITING) {
 279                 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
 280         } else if(state == FL_ERASING) {
 281                 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
 282         }
 283
 284         ndsr = dfc_wait_event(event);
 285
 286         if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
 287                 return(0x1); /* Status Read error */
 288         return 0;
 289 }
 290
 291 /* cmdfunc send commands to the DFC */
 292 static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
 293                         int column, int page_addr)
 294 {
 295         /* register struct nand_chip *this = mtd->priv; */
 296         unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
 297
 298         /* clear the ugly byte read buffer */
 299         bytes_read = -1;
 300         read_buf = 0;
 301
 302         switch (command) {
 303         case NAND_CMD_READ0:
 304                 DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
 305                 dfc_new_cmd();
 306                 ndcb0 = (NAND_CMD_READ0 | (4<<16));
 307                 column >>= 1; /* adjust for 16 bit bus */
 308                 ndcb1 = (((column>>1) & 0xff) |
 309                          ((page_addr<<8) & 0xff00) |
 310                          ((page_addr<<8) & 0xff0000) |
 311                          ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
 312                 event = NDSR_RDDREQ;
 313                 goto write_cmd;
 314         case NAND_CMD_READ1:
 315                 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
 316                 goto end;
 317         case NAND_CMD_READOOB:
 318                 DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
 319                 goto end;
 320         case NAND_CMD_READID:
 321                 dfc_new_cmd();
 322                 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
 323                 ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
 324                 event = NDSR_RDDREQ;
 325                 goto write_cmd;
 326         case NAND_CMD_PAGEPROG:
 327                 /* sent as a multicommand in NAND_CMD_SEQIN */
 328                 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
 329                 goto end;
 330         case NAND_CMD_ERASE1:
 331                 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1,  page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
 332                 dfc_new_cmd();
 333                 ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
 334                 ndcb1 = (page_addr & 0x00ffffff);
 335                 goto write_cmd;
 336         case NAND_CMD_ERASE2:
 337                 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
 338                 goto end;
 339         case NAND_CMD_SEQIN:
 340                 /* send PAGE_PROG command(0x1080) */
 341                 dfc_new_cmd();
 342                 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG,  page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
 343                 ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
 344                 column >>= 1; /* adjust for 16 bit bus */
 345                 ndcb1 = (((column>>1) & 0xff) |
 346                          ((page_addr<<8) & 0xff00) |
 347                          ((page_addr<<8) & 0xff0000) |
 348                          ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
 349                 event = NDSR_WRDREQ;
 350                 goto write_cmd;
 351         case NAND_CMD_STATUS:
 352                 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
 353                 dfc_new_cmd();
 354                 ndcb0 = NAND_CMD_STATUS | (4<<21);
 355                 event = NDSR_RDDREQ;
 356                 goto write_cmd;
 357         case NAND_CMD_RESET:
 358                 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
 359                 ndcb0 = NAND_CMD_RESET | (5<<21);
 360                 event = NDSR_CS0_CMDD;
 361                 goto write_cmd;
 362         default:
 363                 printk("dfc_cmdfunc: error, unsupported command.\n");
 364                 goto end;
 365         }
 366
 367  write_cmd:
 368         NDCB0 = ndcb0;
 369         NDCB0 = ndcb1;
 370         NDCB0 = ndcb2;
 371
 372         /*  wait_event: */
 373         dfc_wait_event(event);
 374  end:
 375         return;
 376 }
 377
 378 static void dfc_gpio_init(void)
 379 {
 380         DFC_DEBUG2("Setting up DFC GPIO's.\n");
 381
 382         /* no idea what is done here, see zylonite.c */
 383         GPIO4 = 0x1;
 384
 385         DF_ALE_WE1 = 0x00000001;
 386         DF_ALE_WE2 = 0x00000001;
 387         DF_nCS0 = 0x00000001;
 388         DF_nCS1 = 0x00000001;
 389         DF_nWE = 0x00000001;
 390         DF_nRE = 0x00000001;
 391         DF_IO0 = 0x00000001;
 392         DF_IO8 = 0x00000001;
 393         DF_IO1 = 0x00000001;
 394         DF_IO9 = 0x00000001;
 395         DF_IO2 = 0x00000001;
 396         DF_IO10 = 0x00000001;
 397         DF_IO3 = 0x00000001;
 398         DF_IO11 = 0x00000001;
 399         DF_IO4 = 0x00000001;
 400         DF_IO12 = 0x00000001;
 401         DF_IO5 = 0x00000001;
 402         DF_IO13 = 0x00000001;
 403         DF_IO6 = 0x00000001;
 404         DF_IO14 = 0x00000001;
 405         DF_IO7 = 0x00000001;
 406         DF_IO15 = 0x00000001;
 407
 408         DF_nWE = 0x1901;
 409         DF_nRE = 0x1901;
 410         DF_CLE_NOE = 0x1900;
 411         DF_ALE_WE1 = 0x1901;
 412         DF_INT_RnB = 0x1900;
 413 }
 414
 415 /*
 416  * Board-specific NAND initialization. The following members of the
 417  * argument are board-specific (per include/linux/mtd/nand_new.h):
 418  * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
 419  * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
 420  * - cmd_ctrl: hardwarespecific function for accesing control-lines
 421  * - dev_ready: hardwarespecific function for  accesing device ready/busy line
 422  * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
 423  *   only be provided if a hardware ECC is available
 424  * - ecc.mode: mode of ecc, see defines
 425  * - chip_delay: chip dependent delay for transfering data from array to
 426  *   read regs (tR)
 427  * - options: various chip options. They can partly be set to inform
 428  *   nand_scan about special functionality. See the defines for further
 429  *   explanation
 430  * Members with a "?" were not set in the merged testing-NAND branch,
 431  * so they are not set here either.
 432  */
 433 int board_nand_init(struct nand_chip *nand)
 434 {
 435         unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
 436
 437         /* set up GPIO Control Registers */
 438         dfc_gpio_init();
 439
 440         /* turn on the NAND Controller Clock (104 MHz @ D0) */
 441         CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
 442
 443 #undef CFG_TIMING_TIGHT
 444 #ifndef CFG_TIMING_TIGHT
 445         tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
 446                   DFC_MAX_tCH);
 447         tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
 448                   DFC_MAX_tCS);
 449         tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
 450                   DFC_MAX_tWH);
 451         tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
 452                   DFC_MAX_tWP);
 453         tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
 454                   DFC_MAX_tRH);
 455         tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
 456                   DFC_MAX_tRP);
 457         tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
 458                  DFC_MAX_tR);
 459         tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
 460                    DFC_MAX_tWHR);
 461         tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
 462                   DFC_MAX_tAR);
 463 #else /* this is the tight timing */
 464
 465         tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
 466                   DFC_MAX_tCH);
 467         tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
 468                   DFC_MAX_tCS);
 469         tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
 470                   DFC_MAX_tWH);
 471         tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
 472                   DFC_MAX_tWP);
 473         tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
 474                   DFC_MAX_tRH);
 475         tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
 476                   DFC_MAX_tRP);
 477         tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
 478                  DFC_MAX_tR);
 479         tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
 480                    DFC_MAX_tWHR);
 481         tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
 482                   DFC_MAX_tAR);
 483 #endif /* CFG_TIMING_TIGHT */
 484
 485
 486         DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
 487
 488         /* tRP value is split in the register */
 489         if(tRP & (1 << 4)) {
 490                 tRP_high = 1;
 491                 tRP &= ~(1 << 4);
 492         } else {
 493                 tRP_high = 0;
 494         }
 495
 496         NDTR0CS0 = (tCH << 19) |
 497                 (tCS << 16) |
 498                 (tWH << 11) |
 499                 (tWP << 8) |
 500                 (tRP_high << 6) |
 501                 (tRH << 3) |
 502                 (tRP << 0);
 503
 504         NDTR1CS0 = (tR << 16) |
 505                 (tWHR << 4) |
 506                 (tAR << 0);
 507
 508         /* If it doesn't work (unlikely) think about:
 509          *  - ecc enable
 510          *  - chip select don't care
 511          *  - read id byte count
 512          *
 513          * Intentionally enabled by not setting bits:
 514          *  - dma (DMA_EN)
 515          *  - page size = 512
 516          *  - cs don't care, see if we can enable later!
 517          *  - row address start position (after second cycle)
 518          *  - pages per block = 32
 519          *  - ND_RDY : clears command buffer
 520          */
 521         /* NDCR_NCSX |          /\* Chip select busy don't care *\/ */
 522
 523         NDCR = (NDCR_SPARE_EN |         /* use the spare area */
 524                 NDCR_DWIDTH_C |         /* 16bit DFC data bus width  */
 525                 NDCR_DWIDTH_M |         /* 16 bit Flash device data bus width */
 526                 (2 << 16) |             /* read id count = 7 ???? mk@tbd */
 527                 NDCR_ND_ARB_EN |        /* enable bus arbiter */
 528                 NDCR_RDYM |             /* flash device ready ir masked */
 529                 NDCR_CS0_PAGEDM |       /* ND_nCSx page done ir masked */
 530                 NDCR_CS1_PAGEDM |
 531                 NDCR_CS0_CMDDM |        /* ND_CSx command done ir masked */
 532                 NDCR_CS1_CMDDM |
 533                 NDCR_CS0_BBDM |         /* ND_CSx bad block detect ir masked */
 534                 NDCR_CS1_BBDM |
 535                 NDCR_DBERRM |           /* double bit error ir masked */
 536                 NDCR_SBERRM |           /* single bit error ir masked */
 537                 NDCR_WRDREQM |          /* write data request ir masked */
 538                 NDCR_RDDREQM |          /* read data request ir masked */
 539                 NDCR_WRCMDREQM);        /* write command request ir masked */
 540
 541
 542         /* wait 10 us due to cmd buffer clear reset */
 543         /*      wait(10); */
 544
 545         nand->cmd_ctrl = dfc_hwcontrol;
 546 /*      nand->dev_ready = dfc_device_ready; */
 547         nand->ecc.mode = NAND_ECC_SOFT;
 548         nand->options = NAND_BUSWIDTH_16;
 549         nand->waitfunc = dfc_wait;
 550         nand->read_byte = dfc_read_byte;
 551         nand->read_word = dfc_read_word;
 552         nand->read_buf = dfc_read_buf;
 553         nand->write_buf = dfc_write_buf;
 554
 555         nand->cmdfunc = dfc_cmdfunc;
 556 /*      nand->autooob = &delta_oob; */
 557         nand->badblock_pattern = &delta_bbt_descr;
 558         return 0;
 559 }
 560
 561 #else
 562  #error "U-Boot legacy NAND support not available for Monahans DFC."
 563 #endif
 564 #endif