1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Andreas Heppel <aheppel@sysgo.de>
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
16 #include <bootretry.h>
21 #include <asm/processor.h>
31 static int pci_byte_size(enum pci_size_t size
)
44 static int pci_field_width(enum pci_size_t size
)
46 return pci_byte_size(size
) * 2;
50 static void pci_show_regs(struct udevice
*dev
, struct pci_reg_info
*regs
)
52 for (; regs
->name
; regs
++) {
55 dm_pci_read_config(dev
, regs
->offset
, &val
, regs
->size
);
56 printf(" %s =%*s%#.*lx\n", regs
->name
,
57 (int)(28 - strlen(regs
->name
)), "",
58 pci_field_width(regs
->size
), val
);
62 static unsigned long pci_read_config(pci_dev_t dev
, int offset
,
71 pci_read_config_byte(dev
, offset
, &val8
);
74 pci_read_config_word(dev
, offset
, &val16
);
78 pci_read_config_dword(dev
, offset
, &val32
);
83 static void pci_show_regs(pci_dev_t dev
, struct pci_reg_info
*regs
)
85 for (; regs
->name
; regs
++) {
86 printf(" %s =%*s%#.*lx\n", regs
->name
,
87 (int)(28 - strlen(regs
->name
)), "",
88 pci_field_width(regs
->size
),
89 pci_read_config(dev
, regs
->offset
, regs
->size
));
95 int pci_bar_show(struct udevice
*dev
)
98 int bar_cnt
, bar_id
, mem_type
;
100 u32 base_low
, base_high
;
101 u32 size_low
, size_high
;
106 dm_pci_read_config8(dev
, PCI_HEADER_TYPE
, &header_type
);
108 if (header_type
== PCI_HEADER_TYPE_CARDBUS
) {
109 printf("CardBus doesn't support BARs\n");
113 bar_cnt
= (header_type
== PCI_HEADER_TYPE_NORMAL
) ? 6 : 2;
115 printf("ID Base Size Width Type\n");
116 printf("----------------------------------------------------------\n");
119 reg_addr
= PCI_BASE_ADDRESS_0
;
121 dm_pci_read_config32(dev
, reg_addr
, &base_low
);
122 dm_pci_write_config32(dev
, reg_addr
, 0xffffffff);
123 dm_pci_read_config32(dev
, reg_addr
, &size_low
);
124 dm_pci_write_config32(dev
, reg_addr
, base_low
);
127 base
= base_low
& ~0xf;
128 size
= size_low
& ~0xf;
130 size_high
= 0xffffffff;
132 prefetchable
= base_low
& PCI_BASE_ADDRESS_MEM_PREFETCH
;
133 is_io
= base_low
& PCI_BASE_ADDRESS_SPACE_IO
;
134 mem_type
= base_low
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
;
136 if (mem_type
== PCI_BASE_ADDRESS_MEM_TYPE_64
) {
137 dm_pci_read_config32(dev
, reg_addr
, &base_high
);
138 dm_pci_write_config32(dev
, reg_addr
, 0xffffffff);
139 dm_pci_read_config32(dev
, reg_addr
, &size_high
);
140 dm_pci_write_config32(dev
, reg_addr
, base_high
);
146 base
= base
| ((u64
)base_high
<< 32);
147 size
= size
| ((u64
)size_high
<< 32);
149 if ((!is_64
&& size_low
) || (is_64
&& size
)) {
151 printf(" %d %#016llx %#016llx %d %s %s\n",
152 bar_id
, (unsigned long long)base
,
153 (unsigned long long)size
, is_64
? 64 : 32,
154 is_io
? "I/O" : "MEM",
155 prefetchable
? "Prefetchable" : "");
166 static struct pci_reg_info regs_start
[] = {
167 { "vendor ID", PCI_SIZE_16
, PCI_VENDOR_ID
},
168 { "device ID", PCI_SIZE_16
, PCI_DEVICE_ID
},
169 { "command register ID", PCI_SIZE_16
, PCI_COMMAND
},
170 { "status register", PCI_SIZE_16
, PCI_STATUS
},
171 { "revision ID", PCI_SIZE_8
, PCI_REVISION_ID
},
175 static struct pci_reg_info regs_rest
[] = {
176 { "sub class code", PCI_SIZE_8
, PCI_CLASS_SUB_CODE
},
177 { "programming interface", PCI_SIZE_8
, PCI_CLASS_PROG
},
178 { "cache line", PCI_SIZE_8
, PCI_CACHE_LINE_SIZE
},
179 { "latency time", PCI_SIZE_8
, PCI_LATENCY_TIMER
},
180 { "header type", PCI_SIZE_8
, PCI_HEADER_TYPE
},
181 { "BIST", PCI_SIZE_8
, PCI_BIST
},
182 { "base address 0", PCI_SIZE_32
, PCI_BASE_ADDRESS_0
},
186 static struct pci_reg_info regs_normal
[] = {
187 { "base address 1", PCI_SIZE_32
, PCI_BASE_ADDRESS_1
},
188 { "base address 2", PCI_SIZE_32
, PCI_BASE_ADDRESS_2
},
189 { "base address 3", PCI_SIZE_32
, PCI_BASE_ADDRESS_3
},
190 { "base address 4", PCI_SIZE_32
, PCI_BASE_ADDRESS_4
},
191 { "base address 5", PCI_SIZE_32
, PCI_BASE_ADDRESS_5
},
192 { "cardBus CIS pointer", PCI_SIZE_32
, PCI_CARDBUS_CIS
},
193 { "sub system vendor ID", PCI_SIZE_16
, PCI_SUBSYSTEM_VENDOR_ID
},
194 { "sub system ID", PCI_SIZE_16
, PCI_SUBSYSTEM_ID
},
195 { "expansion ROM base address", PCI_SIZE_32
, PCI_ROM_ADDRESS
},
196 { "interrupt line", PCI_SIZE_8
, PCI_INTERRUPT_LINE
},
197 { "interrupt pin", PCI_SIZE_8
, PCI_INTERRUPT_PIN
},
198 { "min Grant", PCI_SIZE_8
, PCI_MIN_GNT
},
199 { "max Latency", PCI_SIZE_8
, PCI_MAX_LAT
},
203 static struct pci_reg_info regs_bridge
[] = {
204 { "base address 1", PCI_SIZE_32
, PCI_BASE_ADDRESS_1
},
205 { "primary bus number", PCI_SIZE_8
, PCI_PRIMARY_BUS
},
206 { "secondary bus number", PCI_SIZE_8
, PCI_SECONDARY_BUS
},
207 { "subordinate bus number", PCI_SIZE_8
, PCI_SUBORDINATE_BUS
},
208 { "secondary latency timer", PCI_SIZE_8
, PCI_SEC_LATENCY_TIMER
},
209 { "IO base", PCI_SIZE_8
, PCI_IO_BASE
},
210 { "IO limit", PCI_SIZE_8
, PCI_IO_LIMIT
},
211 { "secondary status", PCI_SIZE_16
, PCI_SEC_STATUS
},
212 { "memory base", PCI_SIZE_16
, PCI_MEMORY_BASE
},
213 { "memory limit", PCI_SIZE_16
, PCI_MEMORY_LIMIT
},
214 { "prefetch memory base", PCI_SIZE_16
, PCI_PREF_MEMORY_BASE
},
215 { "prefetch memory limit", PCI_SIZE_16
, PCI_PREF_MEMORY_LIMIT
},
216 { "prefetch memory base upper", PCI_SIZE_32
, PCI_PREF_BASE_UPPER32
},
217 { "prefetch memory limit upper", PCI_SIZE_32
, PCI_PREF_LIMIT_UPPER32
},
218 { "IO base upper 16 bits", PCI_SIZE_16
, PCI_IO_BASE_UPPER16
},
219 { "IO limit upper 16 bits", PCI_SIZE_16
, PCI_IO_LIMIT_UPPER16
},
220 { "expansion ROM base address", PCI_SIZE_32
, PCI_ROM_ADDRESS1
},
221 { "interrupt line", PCI_SIZE_8
, PCI_INTERRUPT_LINE
},
222 { "interrupt pin", PCI_SIZE_8
, PCI_INTERRUPT_PIN
},
223 { "bridge control", PCI_SIZE_16
, PCI_BRIDGE_CONTROL
},
227 static struct pci_reg_info regs_cardbus
[] = {
228 { "capabilities", PCI_SIZE_8
, PCI_CB_CAPABILITY_LIST
},
229 { "secondary status", PCI_SIZE_16
, PCI_CB_SEC_STATUS
},
230 { "primary bus number", PCI_SIZE_8
, PCI_CB_PRIMARY_BUS
},
231 { "CardBus number", PCI_SIZE_8
, PCI_CB_CARD_BUS
},
232 { "subordinate bus number", PCI_SIZE_8
, PCI_CB_SUBORDINATE_BUS
},
233 { "CardBus latency timer", PCI_SIZE_8
, PCI_CB_LATENCY_TIMER
},
234 { "CardBus memory base 0", PCI_SIZE_32
, PCI_CB_MEMORY_BASE_0
},
235 { "CardBus memory limit 0", PCI_SIZE_32
, PCI_CB_MEMORY_LIMIT_0
},
236 { "CardBus memory base 1", PCI_SIZE_32
, PCI_CB_MEMORY_BASE_1
},
237 { "CardBus memory limit 1", PCI_SIZE_32
, PCI_CB_MEMORY_LIMIT_1
},
238 { "CardBus IO base 0", PCI_SIZE_16
, PCI_CB_IO_BASE_0
},
239 { "CardBus IO base high 0", PCI_SIZE_16
, PCI_CB_IO_BASE_0_HI
},
240 { "CardBus IO limit 0", PCI_SIZE_16
, PCI_CB_IO_LIMIT_0
},
241 { "CardBus IO limit high 0", PCI_SIZE_16
, PCI_CB_IO_LIMIT_0_HI
},
242 { "CardBus IO base 1", PCI_SIZE_16
, PCI_CB_IO_BASE_1
},
243 { "CardBus IO base high 1", PCI_SIZE_16
, PCI_CB_IO_BASE_1_HI
},
244 { "CardBus IO limit 1", PCI_SIZE_16
, PCI_CB_IO_LIMIT_1
},
245 { "CardBus IO limit high 1", PCI_SIZE_16
, PCI_CB_IO_LIMIT_1_HI
},
246 { "interrupt line", PCI_SIZE_8
, PCI_INTERRUPT_LINE
},
247 { "interrupt pin", PCI_SIZE_8
, PCI_INTERRUPT_PIN
},
248 { "bridge control", PCI_SIZE_16
, PCI_CB_BRIDGE_CONTROL
},
249 { "subvendor ID", PCI_SIZE_16
, PCI_CB_SUBSYSTEM_VENDOR_ID
},
250 { "subdevice ID", PCI_SIZE_16
, PCI_CB_SUBSYSTEM_ID
},
251 { "PC Card 16bit base address", PCI_SIZE_32
, PCI_CB_LEGACY_MODE_BASE
},
256 * pci_header_show() - Show the header of the specified PCI device.
258 * @dev: Bus+Device+Function number
261 void pci_header_show(struct udevice
*dev
)
263 void pci_header_show(pci_dev_t dev
)
267 unsigned long class, header_type
;
269 dm_pci_read_config(dev
, PCI_CLASS_CODE
, &class, PCI_SIZE_8
);
270 dm_pci_read_config(dev
, PCI_HEADER_TYPE
, &header_type
, PCI_SIZE_8
);
272 u8
class, header_type
;
274 pci_read_config_byte(dev
, PCI_CLASS_CODE
, &class);
275 pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &header_type
);
277 pci_show_regs(dev
, regs_start
);
278 printf(" class code = 0x%.2x (%s)\n", (int)class,
279 pci_class_str(class));
280 pci_show_regs(dev
, regs_rest
);
282 switch (header_type
& 0x03) {
283 case PCI_HEADER_TYPE_NORMAL
: /* "normal" PCI device */
284 pci_show_regs(dev
, regs_normal
);
286 case PCI_HEADER_TYPE_BRIDGE
: /* PCI-to-PCI bridge */
287 pci_show_regs(dev
, regs_bridge
);
289 case PCI_HEADER_TYPE_CARDBUS
: /* PCI-to-CardBus bridge */
290 pci_show_regs(dev
, regs_cardbus
);
294 printf("unknown header\n");
299 void pciinfo_header(int busnum
, bool short_listing
)
301 printf("Scanning PCI devices on bus %d\n", busnum
);
304 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
305 printf("_____________________________________________________________\n");
311 * pci_header_show_brief() - Show the short-form PCI device header
313 * Reads and prints the header of the specified PCI device in short form.
315 * @dev: PCI device to show
317 static void pci_header_show_brief(struct udevice
*dev
)
319 ulong vendor
, device
;
320 ulong
class, subclass
;
322 dm_pci_read_config(dev
, PCI_VENDOR_ID
, &vendor
, PCI_SIZE_16
);
323 dm_pci_read_config(dev
, PCI_DEVICE_ID
, &device
, PCI_SIZE_16
);
324 dm_pci_read_config(dev
, PCI_CLASS_CODE
, &class, PCI_SIZE_8
);
325 dm_pci_read_config(dev
, PCI_CLASS_SUB_CODE
, &subclass
, PCI_SIZE_8
);
327 printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n",
329 pci_class_str(class), subclass
);
332 static void pciinfo(struct udevice
*bus
, bool short_listing
)
336 pciinfo_header(bus
->seq
, short_listing
);
338 for (device_find_first_child(bus
, &dev
);
340 device_find_next_child(&dev
)) {
341 struct pci_child_platdata
*pplat
;
343 pplat
= dev_get_parent_platdata(dev
);
345 printf("%02x.%02x.%02x ", bus
->seq
,
346 PCI_DEV(pplat
->devfn
), PCI_FUNC(pplat
->devfn
));
347 pci_header_show_brief(dev
);
349 printf("\nFound PCI device %02x.%02x.%02x:\n", bus
->seq
,
350 PCI_DEV(pplat
->devfn
), PCI_FUNC(pplat
->devfn
));
351 pci_header_show(dev
);
359 * pci_header_show_brief() - Show the short-form PCI device header
361 * Reads and prints the header of the specified PCI device in short form.
363 * @dev: Bus+Device+Function number
365 void pci_header_show_brief(pci_dev_t dev
)
370 pci_read_config_word(dev
, PCI_VENDOR_ID
, &vendor
);
371 pci_read_config_word(dev
, PCI_DEVICE_ID
, &device
);
372 pci_read_config_byte(dev
, PCI_CLASS_CODE
, &class);
373 pci_read_config_byte(dev
, PCI_CLASS_SUB_CODE
, &subclass
);
375 printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
377 pci_class_str(class), subclass
);
381 * pciinfo() - Show a list of devices on the PCI bus
383 * Show information about devices on PCI bus. Depending on @short_pci_listing
384 * the output will be more or less exhaustive.
386 * @bus_num: The number of the bus to be scanned
387 * @short_pci_listing: true to use short form, showing only a brief header
390 void pciinfo(int bus_num
, int short_pci_listing
)
392 struct pci_controller
*hose
= pci_bus_to_hose(bus_num
);
395 unsigned char header_type
;
396 unsigned short vendor_id
;
403 pciinfo_header(bus_num
, short_pci_listing
);
405 for (device
= 0; device
< PCI_MAX_PCI_DEVICES
; device
++) {
408 for (function
= 0; function
< PCI_MAX_PCI_FUNCTIONS
;
411 * If this is not a multi-function device, we skip
414 if (function
&& !(header_type
& 0x80))
417 dev
= PCI_BDF(bus_num
, device
, function
);
419 if (pci_skip_dev(hose
, dev
))
422 ret
= pci_read_config_word(dev
, PCI_VENDOR_ID
,
426 if ((vendor_id
== 0xFFFF) || (vendor_id
== 0x0000))
430 pci_read_config_byte(dev
, PCI_HEADER_TYPE
,
434 if (short_pci_listing
) {
435 printf("%02x.%02x.%02x ", bus_num
, device
,
437 pci_header_show_brief(dev
);
439 printf("\nFound PCI device %02x.%02x.%02x:\n",
440 bus_num
, device
, function
);
441 pci_header_show(dev
);
448 printf("Cannot read bus configuration: %d\n", ret
);
453 * get_pci_dev() - Convert the "bus.device.function" identifier into a number
455 * @name: Device string in the form "bus.device.function" where each is in hex
456 * @return encoded pci_dev_t or -1 if the string was invalid
458 static pci_dev_t
get_pci_dev(char *name
)
462 int bdfs
[3] = {0,0,0};
467 for (i
= 0, iold
= 0, n
= 0; i
< len
; i
++) {
468 if (name
[i
] == '.') {
469 memcpy(cnum
, &name
[iold
], i
- iold
);
470 cnum
[i
- iold
] = '\0';
471 bdfs
[n
++] = simple_strtoul(cnum
, NULL
, 16);
475 strcpy(cnum
, &name
[iold
]);
478 bdfs
[n
] = simple_strtoul(cnum
, NULL
, 16);
480 return PCI_BDF(bdfs
[0], bdfs
[1], bdfs
[2]);
484 static int pci_cfg_display(struct udevice
*dev
, ulong addr
,
485 enum pci_size_t size
, ulong length
)
487 static int pci_cfg_display(pci_dev_t bdf
, ulong addr
, enum pci_size_t size
,
491 #define DISP_LINE_LEN 16
492 ulong i
, nbytes
, linebytes
;
496 byte_size
= pci_byte_size(size
);
498 length
= 0x40 / byte_size
; /* Standard PCI config space */
501 * once, and all accesses are with the specified bus width.
503 nbytes
= length
* byte_size
;
505 printf("%08lx:", addr
);
506 linebytes
= (nbytes
> DISP_LINE_LEN
) ? DISP_LINE_LEN
: nbytes
;
507 for (i
= 0; i
< linebytes
; i
+= byte_size
) {
511 dm_pci_read_config(dev
, addr
, &val
, size
);
513 val
= pci_read_config(bdf
, addr
, size
);
515 printf(" %0*lx", pci_field_width(size
), val
);
524 } while (nbytes
> 0);
529 #ifndef CONFIG_DM_PCI
530 static int pci_cfg_write (pci_dev_t bdf
, ulong addr
, ulong size
, ulong value
)
533 pci_write_config_dword(bdf
, addr
, value
);
535 else if (size
== 2) {
536 ushort val
= value
& 0xffff;
537 pci_write_config_word(bdf
, addr
, val
);
540 u_char val
= value
& 0xff;
541 pci_write_config_byte(bdf
, addr
, val
);
548 static int pci_cfg_modify(struct udevice
*dev
, ulong addr
, ulong size
,
549 ulong value
, int incrflag
)
551 static int pci_cfg_modify(pci_dev_t bdf
, ulong addr
, ulong size
, ulong value
,
559 /* Print the address, followed by value. Then accept input for
560 * the next value. A non-converted value exits.
563 printf("%08lx:", addr
);
565 dm_pci_read_config(dev
, addr
, &val
, size
);
567 val
= pci_read_config(bdf
, addr
, size
);
569 printf(" %0*lx", pci_field_width(size
), val
);
571 nbytes
= cli_readline(" ? ");
572 if (nbytes
== 0 || (nbytes
== 1 && console_buffer
[0] == '-')) {
573 /* <CR> pressed as only input, don't modify current
574 * location and move to next. "-" pressed will go back.
577 addr
+= nbytes
? -size
: size
;
579 /* good enough to not time out */
580 bootretry_reset_cmd_timeout();
582 #ifdef CONFIG_BOOT_RETRY_TIME
583 else if (nbytes
== -2) {
584 break; /* timed out, exit the command */
589 i
= simple_strtoul(console_buffer
, &endp
, 16);
590 nbytes
= endp
- console_buffer
;
592 /* good enough to not time out
594 bootretry_reset_cmd_timeout();
596 dm_pci_write_config(dev
, addr
, i
, size
);
598 pci_cfg_write(bdf
, addr
, size
, i
);
610 static const struct pci_flag_info
{
613 } pci_flag_info
[] = {
614 { PCI_REGION_IO
, "io" },
615 { PCI_REGION_PREFETCH
, "prefetch" },
616 { PCI_REGION_SYS_MEMORY
, "sysmem" },
617 { PCI_REGION_RO
, "readonly" },
618 { PCI_REGION_IO
, "io" },
621 static void pci_show_regions(struct udevice
*bus
)
623 struct pci_controller
*hose
= dev_get_uclass_priv(bus
);
624 const struct pci_region
*reg
;
628 printf("Bus '%s' is not a PCI controller\n", bus
->name
);
632 printf("# %-16s %-16s %-16s %s\n", "Bus start", "Phys start", "Size",
634 for (i
= 0, reg
= hose
->regions
; i
< hose
->region_count
; i
++, reg
++) {
635 printf("%d %#016llx %#016llx %#016llx ", i
,
636 (unsigned long long)reg
->bus_start
,
637 (unsigned long long)reg
->phys_start
,
638 (unsigned long long)reg
->size
);
639 if (!(reg
->flags
& PCI_REGION_TYPE
))
641 for (j
= 0; j
< ARRAY_SIZE(pci_flag_info
); j
++) {
642 if (reg
->flags
& pci_flag_info
[j
].flag
)
643 printf("%s ", pci_flag_info
[j
].name
);
650 /* PCI Configuration Space access commands
653 * pci display[.b, .w, .l] bus.device.function} [addr] [len]
654 * pci next[.b, .w, .l] bus.device.function [addr]
655 * pci modify[.b, .w, .l] bus.device.function [addr]
656 * pci write[.b, .w, .l] bus.device.function addr value
658 static int do_pci(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
660 ulong addr
= 0, value
= 0, cmd_size
= 0;
661 enum pci_size_t size
= PCI_SIZE_32
;
663 struct udevice
*dev
, *bus
;
676 case 'd': /* display */
678 case 'm': /* modify */
679 case 'w': /* write */
680 /* Check for a size specification. */
681 cmd_size
= cmd_get_data_size(argv
[1], 4);
682 size
= (cmd_size
== 4) ? PCI_SIZE_32
: cmd_size
- 1;
684 addr
= simple_strtoul(argv
[3], NULL
, 16);
686 value
= simple_strtoul(argv
[4], NULL
, 16);
687 case 'h': /* header */
693 if ((bdf
= get_pci_dev(argv
[2])) == -1)
696 #if defined(CONFIG_DM_PCI)
701 case 'r': /* no break */
702 default: /* scan bus */
703 value
= 1; /* short listing */
705 if (cmd
!= 'r' && argv
[argc
-1][0] == 'l') {
710 busnum
= simple_strtoul(argv
[1], NULL
, 16);
713 ret
= uclass_get_device_by_seq(UCLASS_PCI
, busnum
, &bus
);
715 printf("No such bus\n");
716 return CMD_RET_FAILURE
;
719 pci_show_regions(bus
);
723 pciinfo(busnum
, value
);
729 ret
= dm_pci_bus_find_bdf(bdf
, &dev
);
731 printf("No such device\n");
732 return CMD_RET_FAILURE
;
738 switch (argv
[1][0]) {
739 case 'h': /* header */
740 pci_header_show(dev
);
742 case 'd': /* display */
743 return pci_cfg_display(dev
, addr
, size
, value
);
747 ret
= pci_cfg_modify(dev
, addr
, size
, value
, 0);
749 case 'm': /* modify */
752 ret
= pci_cfg_modify(dev
, addr
, size
, value
, 1);
754 case 'w': /* write */
758 ret
= dm_pci_write_config(dev
, addr
, value
, size
);
760 ret
= pci_cfg_write(dev
, addr
, size
, value
);
766 return pci_bar_show(dev
);
775 return CMD_RET_USAGE
;
778 /***************************************************/
780 #ifdef CONFIG_SYS_LONGHELP
781 static char pci_help_text
[] =
783 " - short or long list of PCI devices on bus 'bus'\n"
784 #if defined(CONFIG_DM_PCI)
786 " - Enumerate PCI buses\n"
789 " - show header of PCI device 'bus.device.function'\n"
792 " - show BARs base and size for device b.d.f'\n"
794 " - show PCI regions\n"
796 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
797 " - display PCI configuration space (CFG)\n"
798 "pci next[.b, .w, .l] b.d.f address\n"
799 " - modify, read and keep CFG address\n"
800 "pci modify[.b, .w, .l] b.d.f address\n"
801 " - modify, auto increment CFG address\n"
802 "pci write[.b, .w, .l] b.d.f address value\n"
803 " - write to CFG address";
808 "list and access PCI Configuration Space", pci_help_text