2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <bootretry.h>
22 #include <asm/processor.h>
32 static int pci_byte_size(enum pci_size_t size
)
45 static int pci_field_width(enum pci_size_t size
)
47 return pci_byte_size(size
) * 2;
51 static void pci_show_regs(struct udevice
*dev
, struct pci_reg_info
*regs
)
53 for (; regs
->name
; regs
++) {
56 dm_pci_read_config(dev
, regs
->offset
, &val
, regs
->size
);
57 printf(" %s =%*s%#.*lx\n", regs
->name
,
58 (int)(28 - strlen(regs
->name
)), "",
59 pci_field_width(regs
->size
), val
);
63 static unsigned long pci_read_config(pci_dev_t dev
, int offset
,
72 pci_read_config_byte(dev
, offset
, &val8
);
75 pci_read_config_word(dev
, offset
, &val16
);
79 pci_read_config_dword(dev
, offset
, &val32
);
84 static void pci_show_regs(pci_dev_t dev
, struct pci_reg_info
*regs
)
86 for (; regs
->name
; regs
++) {
87 printf(" %s =%*s%#.*lx\n", regs
->name
,
88 (int)(28 - strlen(regs
->name
)), "",
89 pci_field_width(regs
->size
),
90 pci_read_config(dev
, regs
->offset
, regs
->size
));
95 static struct pci_reg_info regs_start
[] = {
96 { "vendor ID", PCI_SIZE_16
, PCI_VENDOR_ID
},
97 { "device ID", PCI_SIZE_16
, PCI_DEVICE_ID
},
98 { "command register ID", PCI_SIZE_16
, PCI_COMMAND
},
99 { "status register", PCI_SIZE_16
, PCI_STATUS
},
100 { "revision ID", PCI_SIZE_8
, PCI_REVISION_ID
},
104 static struct pci_reg_info regs_rest
[] = {
105 { "sub class code", PCI_SIZE_8
, PCI_CLASS_SUB_CODE
},
106 { "programming interface", PCI_SIZE_8
, PCI_CLASS_PROG
},
107 { "cache line", PCI_SIZE_8
, PCI_CACHE_LINE_SIZE
},
108 { "latency time", PCI_SIZE_8
, PCI_LATENCY_TIMER
},
109 { "header type", PCI_SIZE_8
, PCI_HEADER_TYPE
},
110 { "BIST", PCI_SIZE_8
, PCI_BIST
},
111 { "base address 0", PCI_SIZE_32
, PCI_BASE_ADDRESS_0
},
115 static struct pci_reg_info regs_normal
[] = {
116 { "base address 1", PCI_SIZE_32
, PCI_BASE_ADDRESS_1
},
117 { "base address 2", PCI_SIZE_32
, PCI_BASE_ADDRESS_2
},
118 { "base address 3", PCI_SIZE_32
, PCI_BASE_ADDRESS_3
},
119 { "base address 4", PCI_SIZE_32
, PCI_BASE_ADDRESS_4
},
120 { "base address 5", PCI_SIZE_32
, PCI_BASE_ADDRESS_5
},
121 { "cardBus CIS pointer", PCI_SIZE_32
, PCI_CARDBUS_CIS
},
122 { "sub system vendor ID", PCI_SIZE_16
, PCI_SUBSYSTEM_VENDOR_ID
},
123 { "sub system ID", PCI_SIZE_16
, PCI_SUBSYSTEM_ID
},
124 { "expansion ROM base address", PCI_SIZE_32
, PCI_ROM_ADDRESS
},
125 { "interrupt line", PCI_SIZE_8
, PCI_INTERRUPT_LINE
},
126 { "interrupt pin", PCI_SIZE_8
, PCI_INTERRUPT_PIN
},
127 { "min Grant", PCI_SIZE_8
, PCI_MIN_GNT
},
128 { "max Latency", PCI_SIZE_8
, PCI_MAX_LAT
},
132 static struct pci_reg_info regs_bridge
[] = {
133 { "base address 1", PCI_SIZE_32
, PCI_BASE_ADDRESS_1
},
134 { "primary bus number", PCI_SIZE_8
, PCI_PRIMARY_BUS
},
135 { "secondary bus number", PCI_SIZE_8
, PCI_SECONDARY_BUS
},
136 { "subordinate bus number", PCI_SIZE_8
, PCI_SUBORDINATE_BUS
},
137 { "secondary latency timer", PCI_SIZE_8
, PCI_SEC_LATENCY_TIMER
},
138 { "IO base", PCI_SIZE_8
, PCI_IO_BASE
},
139 { "IO limit", PCI_SIZE_8
, PCI_IO_LIMIT
},
140 { "secondary status", PCI_SIZE_16
, PCI_SEC_STATUS
},
141 { "memory base", PCI_SIZE_16
, PCI_MEMORY_BASE
},
142 { "memory limit", PCI_SIZE_16
, PCI_MEMORY_LIMIT
},
143 { "prefetch memory base", PCI_SIZE_16
, PCI_PREF_MEMORY_BASE
},
144 { "prefetch memory limit", PCI_SIZE_16
, PCI_PREF_MEMORY_LIMIT
},
145 { "prefetch memory base upper", PCI_SIZE_32
, PCI_PREF_BASE_UPPER32
},
146 { "prefetch memory limit upper", PCI_SIZE_32
, PCI_PREF_LIMIT_UPPER32
},
147 { "IO base upper 16 bits", PCI_SIZE_16
, PCI_IO_BASE_UPPER16
},
148 { "IO limit upper 16 bits", PCI_SIZE_16
, PCI_IO_LIMIT_UPPER16
},
149 { "expansion ROM base address", PCI_SIZE_32
, PCI_ROM_ADDRESS1
},
150 { "interrupt line", PCI_SIZE_8
, PCI_INTERRUPT_LINE
},
151 { "interrupt pin", PCI_SIZE_8
, PCI_INTERRUPT_PIN
},
152 { "bridge control", PCI_SIZE_16
, PCI_BRIDGE_CONTROL
},
156 static struct pci_reg_info regs_cardbus
[] = {
157 { "capabilities", PCI_SIZE_8
, PCI_CB_CAPABILITY_LIST
},
158 { "secondary status", PCI_SIZE_16
, PCI_CB_SEC_STATUS
},
159 { "primary bus number", PCI_SIZE_8
, PCI_CB_PRIMARY_BUS
},
160 { "CardBus number", PCI_SIZE_8
, PCI_CB_CARD_BUS
},
161 { "subordinate bus number", PCI_SIZE_8
, PCI_CB_SUBORDINATE_BUS
},
162 { "CardBus latency timer", PCI_SIZE_8
, PCI_CB_LATENCY_TIMER
},
163 { "CardBus memory base 0", PCI_SIZE_32
, PCI_CB_MEMORY_BASE_0
},
164 { "CardBus memory limit 0", PCI_SIZE_32
, PCI_CB_MEMORY_LIMIT_0
},
165 { "CardBus memory base 1", PCI_SIZE_32
, PCI_CB_MEMORY_BASE_1
},
166 { "CardBus memory limit 1", PCI_SIZE_32
, PCI_CB_MEMORY_LIMIT_1
},
167 { "CardBus IO base 0", PCI_SIZE_16
, PCI_CB_IO_BASE_0
},
168 { "CardBus IO base high 0", PCI_SIZE_16
, PCI_CB_IO_BASE_0_HI
},
169 { "CardBus IO limit 0", PCI_SIZE_16
, PCI_CB_IO_LIMIT_0
},
170 { "CardBus IO limit high 0", PCI_SIZE_16
, PCI_CB_IO_LIMIT_0_HI
},
171 { "CardBus IO base 1", PCI_SIZE_16
, PCI_CB_IO_BASE_1
},
172 { "CardBus IO base high 1", PCI_SIZE_16
, PCI_CB_IO_BASE_1_HI
},
173 { "CardBus IO limit 1", PCI_SIZE_16
, PCI_CB_IO_LIMIT_1
},
174 { "CardBus IO limit high 1", PCI_SIZE_16
, PCI_CB_IO_LIMIT_1_HI
},
175 { "interrupt line", PCI_SIZE_8
, PCI_INTERRUPT_LINE
},
176 { "interrupt pin", PCI_SIZE_8
, PCI_INTERRUPT_PIN
},
177 { "bridge control", PCI_SIZE_16
, PCI_CB_BRIDGE_CONTROL
},
178 { "subvendor ID", PCI_SIZE_16
, PCI_CB_SUBSYSTEM_VENDOR_ID
},
179 { "subdevice ID", PCI_SIZE_16
, PCI_CB_SUBSYSTEM_ID
},
180 { "PC Card 16bit base address", PCI_SIZE_32
, PCI_CB_LEGACY_MODE_BASE
},
185 * pci_header_show() - Show the header of the specified PCI device.
187 * @dev: Bus+Device+Function number
190 void pci_header_show(struct udevice
*dev
)
192 void pci_header_show(pci_dev_t dev
)
196 unsigned long class, header_type
;
198 dm_pci_read_config(dev
, PCI_CLASS_CODE
, &class, PCI_SIZE_8
);
199 dm_pci_read_config(dev
, PCI_HEADER_TYPE
, &header_type
, PCI_SIZE_8
);
201 u8
class, header_type
;
203 pci_read_config_byte(dev
, PCI_CLASS_CODE
, &class);
204 pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &header_type
);
206 pci_show_regs(dev
, regs_start
);
207 printf(" class code = 0x%.2x (%s)\n", (int)class,
208 pci_class_str(class));
209 pci_show_regs(dev
, regs_rest
);
211 switch (header_type
& 0x03) {
212 case PCI_HEADER_TYPE_NORMAL
: /* "normal" PCI device */
213 pci_show_regs(dev
, regs_normal
);
215 case PCI_HEADER_TYPE_BRIDGE
: /* PCI-to-PCI bridge */
216 pci_show_regs(dev
, regs_bridge
);
218 case PCI_HEADER_TYPE_CARDBUS
: /* PCI-to-CardBus bridge */
219 pci_show_regs(dev
, regs_cardbus
);
223 printf("unknown header\n");
228 void pciinfo_header(int busnum
, bool short_listing
)
230 printf("Scanning PCI devices on bus %d\n", busnum
);
233 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
234 printf("_____________________________________________________________\n");
240 * pci_header_show_brief() - Show the short-form PCI device header
242 * Reads and prints the header of the specified PCI device in short form.
244 * @dev: PCI device to show
246 static void pci_header_show_brief(struct udevice
*dev
)
248 ulong vendor
, device
;
249 ulong
class, subclass
;
251 dm_pci_read_config(dev
, PCI_VENDOR_ID
, &vendor
, PCI_SIZE_16
);
252 dm_pci_read_config(dev
, PCI_DEVICE_ID
, &device
, PCI_SIZE_16
);
253 dm_pci_read_config(dev
, PCI_CLASS_CODE
, &class, PCI_SIZE_8
);
254 dm_pci_read_config(dev
, PCI_CLASS_SUB_CODE
, &subclass
, PCI_SIZE_8
);
256 printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n",
258 pci_class_str(class), subclass
);
261 static void pciinfo(struct udevice
*bus
, bool short_listing
)
265 pciinfo_header(bus
->seq
, short_listing
);
267 for (device_find_first_child(bus
, &dev
);
269 device_find_next_child(&dev
)) {
270 struct pci_child_platdata
*pplat
;
272 pplat
= dev_get_parent_platdata(dev
);
274 printf("%02x.%02x.%02x ", bus
->seq
,
275 PCI_DEV(pplat
->devfn
), PCI_FUNC(pplat
->devfn
));
276 pci_header_show_brief(dev
);
278 printf("\nFound PCI device %02x.%02x.%02x:\n", bus
->seq
,
279 PCI_DEV(pplat
->devfn
), PCI_FUNC(pplat
->devfn
));
280 pci_header_show(dev
);
288 * pci_header_show_brief() - Show the short-form PCI device header
290 * Reads and prints the header of the specified PCI device in short form.
292 * @dev: Bus+Device+Function number
294 void pci_header_show_brief(pci_dev_t dev
)
299 pci_read_config_word(dev
, PCI_VENDOR_ID
, &vendor
);
300 pci_read_config_word(dev
, PCI_DEVICE_ID
, &device
);
301 pci_read_config_byte(dev
, PCI_CLASS_CODE
, &class);
302 pci_read_config_byte(dev
, PCI_CLASS_SUB_CODE
, &subclass
);
304 printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
306 pci_class_str(class), subclass
);
310 * pciinfo() - Show a list of devices on the PCI bus
312 * Show information about devices on PCI bus. Depending on @short_pci_listing
313 * the output will be more or less exhaustive.
315 * @bus_num: The number of the bus to be scanned
316 * @short_pci_listing: true to use short form, showing only a brief header
319 void pciinfo(int bus_num
, int short_pci_listing
)
321 struct pci_controller
*hose
= pci_bus_to_hose(bus_num
);
324 unsigned char header_type
;
325 unsigned short vendor_id
;
332 pciinfo_header(bus_num
, short_pci_listing
);
334 for (device
= 0; device
< PCI_MAX_PCI_DEVICES
; device
++) {
337 for (function
= 0; function
< PCI_MAX_PCI_FUNCTIONS
;
340 * If this is not a multi-function device, we skip
343 if (function
&& !(header_type
& 0x80))
346 dev
= PCI_BDF(bus_num
, device
, function
);
348 if (pci_skip_dev(hose
, dev
))
351 ret
= pci_read_config_word(dev
, PCI_VENDOR_ID
,
355 if ((vendor_id
== 0xFFFF) || (vendor_id
== 0x0000))
359 pci_read_config_byte(dev
, PCI_HEADER_TYPE
,
363 if (short_pci_listing
) {
364 printf("%02x.%02x.%02x ", bus_num
, device
,
366 pci_header_show_brief(dev
);
368 printf("\nFound PCI device %02x.%02x.%02x:\n",
369 bus_num
, device
, function
);
370 pci_header_show(dev
);
377 printf("Cannot read bus configuration: %d\n", ret
);
382 * get_pci_dev() - Convert the "bus.device.function" identifier into a number
384 * @name: Device string in the form "bus.device.function" where each is in hex
385 * @return encoded pci_dev_t or -1 if the string was invalid
387 static pci_dev_t
get_pci_dev(char *name
)
391 int bdfs
[3] = {0,0,0};
396 for (i
= 0, iold
= 0, n
= 0; i
< len
; i
++) {
397 if (name
[i
] == '.') {
398 memcpy(cnum
, &name
[iold
], i
- iold
);
399 cnum
[i
- iold
] = '\0';
400 bdfs
[n
++] = simple_strtoul(cnum
, NULL
, 16);
404 strcpy(cnum
, &name
[iold
]);
407 bdfs
[n
] = simple_strtoul(cnum
, NULL
, 16);
409 return PCI_BDF(bdfs
[0], bdfs
[1], bdfs
[2]);
413 static int pci_cfg_display(struct udevice
*dev
, ulong addr
,
414 enum pci_size_t size
, ulong length
)
416 static int pci_cfg_display(pci_dev_t bdf
, ulong addr
, enum pci_size_t size
,
420 #define DISP_LINE_LEN 16
421 ulong i
, nbytes
, linebytes
;
425 byte_size
= pci_byte_size(size
);
427 length
= 0x40 / byte_size
; /* Standard PCI config space */
430 * once, and all accesses are with the specified bus width.
432 nbytes
= length
* byte_size
;
434 printf("%08lx:", addr
);
435 linebytes
= (nbytes
> DISP_LINE_LEN
) ? DISP_LINE_LEN
: nbytes
;
436 for (i
= 0; i
< linebytes
; i
+= byte_size
) {
440 dm_pci_read_config(dev
, addr
, &val
, size
);
442 val
= pci_read_config(bdf
, addr
, size
);
444 printf(" %0*lx", pci_field_width(size
), val
);
453 } while (nbytes
> 0);
458 #ifndef CONFIG_DM_PCI
459 static int pci_cfg_write (pci_dev_t bdf
, ulong addr
, ulong size
, ulong value
)
462 pci_write_config_dword(bdf
, addr
, value
);
464 else if (size
== 2) {
465 ushort val
= value
& 0xffff;
466 pci_write_config_word(bdf
, addr
, val
);
469 u_char val
= value
& 0xff;
470 pci_write_config_byte(bdf
, addr
, val
);
477 static int pci_cfg_modify(struct udevice
*dev
, ulong addr
, ulong size
,
478 ulong value
, int incrflag
)
480 static int pci_cfg_modify(pci_dev_t bdf
, ulong addr
, ulong size
, ulong value
,
488 /* Print the address, followed by value. Then accept input for
489 * the next value. A non-converted value exits.
492 printf("%08lx:", addr
);
494 dm_pci_read_config(dev
, addr
, &val
, size
);
496 val
= pci_read_config(bdf
, addr
, size
);
498 printf(" %0*lx", pci_field_width(size
), val
);
500 nbytes
= cli_readline(" ? ");
501 if (nbytes
== 0 || (nbytes
== 1 && console_buffer
[0] == '-')) {
502 /* <CR> pressed as only input, don't modify current
503 * location and move to next. "-" pressed will go back.
506 addr
+= nbytes
? -size
: size
;
508 /* good enough to not time out */
509 bootretry_reset_cmd_timeout();
511 #ifdef CONFIG_BOOT_RETRY_TIME
512 else if (nbytes
== -2) {
513 break; /* timed out, exit the command */
518 i
= simple_strtoul(console_buffer
, &endp
, 16);
519 nbytes
= endp
- console_buffer
;
521 /* good enough to not time out
523 bootretry_reset_cmd_timeout();
525 dm_pci_write_config(dev
, addr
, i
, size
);
527 pci_cfg_write(bdf
, addr
, size
, i
);
538 /* PCI Configuration Space access commands
541 * pci display[.b, .w, .l] bus.device.function} [addr] [len]
542 * pci next[.b, .w, .l] bus.device.function [addr]
543 * pci modify[.b, .w, .l] bus.device.function [addr]
544 * pci write[.b, .w, .l] bus.device.function addr value
546 static int do_pci(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
548 ulong addr
= 0, value
= 0, cmd_size
= 0;
549 enum pci_size_t size
= PCI_SIZE_32
;
551 struct udevice
*dev
, *bus
;
564 case 'd': /* display */
566 case 'm': /* modify */
567 case 'w': /* write */
568 /* Check for a size specification. */
569 cmd_size
= cmd_get_data_size(argv
[1], 4);
570 size
= (cmd_size
== 4) ? PCI_SIZE_32
: cmd_size
- 1;
572 addr
= simple_strtoul(argv
[3], NULL
, 16);
574 value
= simple_strtoul(argv
[4], NULL
, 16);
575 case 'h': /* header */
578 if ((bdf
= get_pci_dev(argv
[2])) == -1)
581 #if defined(CONFIG_CMD_PCI_ENUM) || defined(CONFIG_DM_PCI)
586 default: /* scan bus */
587 value
= 1; /* short listing */
589 if (argv
[argc
-1][0] == 'l') {
594 busnum
= simple_strtoul(argv
[1], NULL
, 16);
597 ret
= uclass_get_device_by_seq(UCLASS_PCI
, busnum
, &bus
);
599 printf("No such bus\n");
600 return CMD_RET_FAILURE
;
604 pciinfo(busnum
, value
);
610 ret
= dm_pci_bus_find_bdf(bdf
, &dev
);
612 printf("No such device\n");
613 return CMD_RET_FAILURE
;
619 switch (argv
[1][0]) {
620 case 'h': /* header */
621 pci_header_show(dev
);
623 case 'd': /* display */
624 return pci_cfg_display(dev
, addr
, size
, value
);
628 ret
= pci_cfg_modify(dev
, addr
, size
, value
, 0);
630 case 'm': /* modify */
633 ret
= pci_cfg_modify(dev
, addr
, size
, value
, 1);
635 case 'w': /* write */
639 ret
= dm_pci_write_config(dev
, addr
, value
, size
);
641 ret
= pci_cfg_write(dev
, addr
, size
, value
);
651 return CMD_RET_USAGE
;
654 /***************************************************/
656 #ifdef CONFIG_SYS_LONGHELP
657 static char pci_help_text
[] =
659 " - short or long list of PCI devices on bus 'bus'\n"
660 #if defined(CONFIG_CMD_PCI_ENUM) || defined(CONFIG_DM_PCI)
662 " - Enumerate PCI buses\n"
665 " - show header of PCI device 'bus.device.function'\n"
666 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
667 " - display PCI configuration space (CFG)\n"
668 "pci next[.b, .w, .l] b.d.f address\n"
669 " - modify, read and keep CFG address\n"
670 "pci modify[.b, .w, .l] b.d.f address\n"
671 " - modify, auto increment CFG address\n"
672 "pci write[.b, .w, .l] b.d.f address value\n"
673 " - write to CFG address";
678 "list and access PCI Configuration Space", pci_help_text