3 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
6 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <common.h> /* core U-Boot definitions */
29 #include <ACEX1K.h> /* ACEX device family */
31 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_ACEX1K)
33 /* Define FPGA_DEBUG to get debug printf's */
35 #define PRINTF(fmt,args...) printf (fmt ,##args)
37 #define PRINTF(fmt,args...)
40 /* Note: The assumption is that we cannot possibly run fast enough to
41 * overrun the device (the Slave Parallel mode can free run at 50MHz).
42 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
43 * the board config file to slow things down.
45 #ifndef CONFIG_FPGA_DELAY
46 #define CONFIG_FPGA_DELAY()
50 #define CFG_FPGA_WAIT CFG_HZ/10 /* 100 ms */
53 static int ACEX1K_ps_load( Altera_desc
*desc
, void *buf
, size_t bsize
);
54 static int ACEX1K_ps_dump( Altera_desc
*desc
, void *buf
, size_t bsize
);
55 /* static int ACEX1K_ps_info( Altera_desc *desc ); */
56 static int ACEX1K_ps_reloc( Altera_desc
*desc
, ulong reloc_offset
);
58 /* ------------------------------------------------------------------------- */
59 /* ACEX1K Generic Implementation */
60 int ACEX1K_load (Altera_desc
* desc
, void *buf
, size_t bsize
)
62 int ret_val
= FPGA_FAIL
;
64 switch (desc
->iface
) {
66 PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__
);
67 ret_val
= ACEX1K_ps_load (desc
, buf
, bsize
);
70 /* Add new interface types here */
73 printf ("%s: Unsupported interface type, %d\n",
74 __FUNCTION__
, desc
->iface
);
80 int ACEX1K_dump (Altera_desc
* desc
, void *buf
, size_t bsize
)
82 int ret_val
= FPGA_FAIL
;
84 switch (desc
->iface
) {
86 PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__
);
87 ret_val
= ACEX1K_ps_dump (desc
, buf
, bsize
);
90 /* Add new interface types here */
93 printf ("%s: Unsupported interface type, %d\n",
94 __FUNCTION__
, desc
->iface
);
100 int ACEX1K_info( Altera_desc
*desc
)
106 int ACEX1K_reloc (Altera_desc
* desc
, ulong reloc_offset
)
108 int ret_val
= FPGA_FAIL
; /* assume a failure */
110 if (desc
->family
!= Altera_ACEX1K
) {
111 printf ("%s: Unsupported family type, %d\n",
112 __FUNCTION__
, desc
->family
);
115 switch (desc
->iface
) {
117 ret_val
= ACEX1K_ps_reloc (desc
, reloc_offset
);
120 /* Add new interface types here */
123 printf ("%s: Unsupported interface type, %d\n",
124 __FUNCTION__
, desc
->iface
);
131 /* ------------------------------------------------------------------------- */
132 /* ACEX1K Passive Serial Generic Implementation */
134 static int ACEX1K_ps_load (Altera_desc
* desc
, void *buf
, size_t bsize
)
136 int ret_val
= FPGA_FAIL
; /* assume the worst */
137 Altera_ACEX1K_Passive_Serial_fns
*fn
= desc
->iface_fns
;
140 PRINTF ("%s: start with interface functions @ 0x%p\n",
144 size_t bytecount
= 0;
145 unsigned char *data
= (unsigned char *) buf
;
146 int cookie
= desc
->cookie
; /* make a local copy */
147 unsigned long ts
; /* timestamp */
149 PRINTF ("%s: Function Table:\n"
157 __FUNCTION__
, &fn
, fn
, fn
->config
, fn
->status
,
158 fn
->clk
, fn
->data
, fn
->done
);
159 #ifdef CFG_FPGA_PROG_FEEDBACK
160 printf ("Loading FPGA Device %d...", cookie
);
164 * Run the pre configuration function if there is one.
170 /* Establish the initial state */
171 (*fn
->config
) (TRUE
, TRUE
, cookie
); /* Assert nCONFIG */
173 udelay(2); /* T_cfg > 2us */
175 /* nSTATUS should be asserted now */
176 (*fn
->done
) (cookie
);
177 if ( !(*fn
->status
) (cookie
) ) {
178 puts ("** nSTATUS is not asserted.\n");
179 (*fn
->abort
) (cookie
);
183 (*fn
->config
) (FALSE
, TRUE
, cookie
); /* Deassert nCONFIG */
184 udelay(2); /* T_cf2st1 < 4us */
186 /* Wait for nSTATUS to be released (i.e. deasserted) */
187 ts
= get_timer (0); /* get current time */
189 CONFIG_FPGA_DELAY ();
190 if (get_timer (ts
) > CFG_FPGA_WAIT
) { /* check the time */
191 puts ("** Timeout waiting for STATUS to go high.\n");
192 (*fn
->abort
) (cookie
);
195 (*fn
->done
) (cookie
);
196 } while ((*fn
->status
) (cookie
));
198 /* Get ready for the burn */
199 CONFIG_FPGA_DELAY ();
202 while (bytecount
< bsize
) {
204 #ifdef CFG_FPGA_CHECK_CTRLC
206 (*fn
->abort
) (cookie
);
210 /* Altera detects an error if INIT goes low (active)
211 while DONE is low (inactive) */
212 #if 0 /* not yet implemented */
213 if ((*fn
->done
) (cookie
) == 0 && (*fn
->init
) (cookie
)) {
214 puts ("** CRC error during FPGA load.\n");
215 (*fn
->abort
) (cookie
);
219 val
= data
[bytecount
++ ];
222 /* Deassert the clock */
223 (*fn
->clk
) (FALSE
, TRUE
, cookie
);
224 CONFIG_FPGA_DELAY ();
226 (*fn
->data
) ( (val
& 0x01), TRUE
, cookie
);
227 CONFIG_FPGA_DELAY ();
228 /* Assert the clock */
229 (*fn
->clk
) (TRUE
, TRUE
, cookie
);
230 CONFIG_FPGA_DELAY ();
235 #ifdef CFG_FPGA_PROG_FEEDBACK
236 if (bytecount
% (bsize
/ 40) == 0)
237 putc ('.'); /* let them know we are alive */
241 CONFIG_FPGA_DELAY ();
243 #ifdef CFG_FPGA_PROG_FEEDBACK
244 putc (' '); /* terminate the dotted line */
248 * Checking FPGA's CONF_DONE signal - correctly booted ?
251 if ( ! (*fn
->done
) (cookie
) ) {
252 puts ("** Booting failed! CONF_DONE is still deasserted.\n");
253 (*fn
->abort
) (cookie
);
258 * "DCLK must be clocked an additional 10 times fpr ACEX 1K..."
261 for (i
= 0; i
< 12; i
++) {
262 CONFIG_FPGA_DELAY ();
263 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
264 CONFIG_FPGA_DELAY ();
265 (*fn
->clk
) (FALSE
, TRUE
, cookie
); /* Deassert the clock pin */
268 ret_val
= FPGA_SUCCESS
;
270 #ifdef CFG_FPGA_PROG_FEEDBACK
271 if (ret_val
== FPGA_SUCCESS
) {
278 (*fn
->post
) (cookie
);
281 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
287 static int ACEX1K_ps_dump (Altera_desc
* desc
, void *buf
, size_t bsize
)
289 /* Readback is only available through the Slave Parallel and */
290 /* boundary-scan interfaces. */
291 printf ("%s: Passive Serial Dumping is unavailable\n",
296 static int ACEX1K_ps_reloc (Altera_desc
* desc
, ulong reloc_offset
)
298 int ret_val
= FPGA_FAIL
; /* assume the worst */
299 Altera_ACEX1K_Passive_Serial_fns
*fn_r
, *fn
=
300 (Altera_ACEX1K_Passive_Serial_fns
*) (desc
->iface_fns
);
305 /* Get the relocated table address */
306 addr
= (ulong
) fn
+ reloc_offset
;
307 fn_r
= (Altera_ACEX1K_Passive_Serial_fns
*) addr
;
309 if (!fn_r
->relocated
) {
311 if (memcmp (fn_r
, fn
,
312 sizeof (Altera_ACEX1K_Passive_Serial_fns
))
314 /* good copy of the table, fix the descriptor pointer */
315 desc
->iface_fns
= fn_r
;
317 PRINTF ("%s: Invalid function table at 0x%p\n",
322 PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__
,
325 addr
= (ulong
) (fn
->pre
) + reloc_offset
;
326 fn_r
->pre
= (Altera_pre_fn
) addr
;
328 addr
= (ulong
) (fn
->config
) + reloc_offset
;
329 fn_r
->config
= (Altera_config_fn
) addr
;
331 addr
= (ulong
) (fn
->status
) + reloc_offset
;
332 fn_r
->status
= (Altera_status_fn
) addr
;
334 addr
= (ulong
) (fn
->done
) + reloc_offset
;
335 fn_r
->done
= (Altera_done_fn
) addr
;
337 addr
= (ulong
) (fn
->clk
) + reloc_offset
;
338 fn_r
->clk
= (Altera_clk_fn
) addr
;
340 addr
= (ulong
) (fn
->data
) + reloc_offset
;
341 fn_r
->data
= (Altera_data_fn
) addr
;
343 addr
= (ulong
) (fn
->abort
) + reloc_offset
;
344 fn_r
->abort
= (Altera_abort_fn
) addr
;
346 addr
= (ulong
) (fn
->post
) + reloc_offset
;
347 fn_r
->post
= (Altera_post_fn
) addr
;
349 fn_r
->relocated
= TRUE
;
352 /* this table has already been moved */
353 /* XXX - should check to see if the descriptor is correct */
354 desc
->iface_fns
= fn_r
;
357 ret_val
= FPGA_SUCCESS
;
359 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
366 #endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_ACEX1K */