common/cmd_fpga.c

   1 /*
   2  * (C) Copyright 2000, 2001
   3  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  */
  24
  25 /*
  26  *  FPGA support
  27  */
  28 #include <common.h>
  29 #include <command.h>
  30 #if defined(CONFIG_CMD_NET)
  31 #include <net.h>
  32 #endif
  33 #include <fpga.h>
  34 #include <malloc.h>
  35
  36 /* Local functions */
  37 static int fpga_get_op (char *opstr);
  38
  39 /* Local defines */
  40 #define FPGA_NONE   -1
  41 #define FPGA_INFO   0
  42 #define FPGA_LOAD   1
  43 #define FPGA_LOADB  2
  44 #define FPGA_DUMP   3
  45 #define FPGA_LOADMK 4
  46
  47 /* Convert bitstream data and load into the fpga */
  48 int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
  49 {
  50 #if defined(CONFIG_FPGA_XILINX)
  51         unsigned int length;
  52         unsigned int swapsize;
  53         char buffer[80];
  54         unsigned char *dataptr;
  55         unsigned int i;
  56         int rc;
  57
  58         dataptr = (unsigned char *)fpgadata;
  59
  60         /* skip the first bytes of the bitsteam, their meaning is unknown */
  61         length = (*dataptr << 8) + *(dataptr+1);
  62         dataptr+=2;
  63         dataptr+=length;
  64
  65         /* get design name (identifier, length, string) */
  66         length = (*dataptr << 8) + *(dataptr+1);
  67         dataptr+=2;
  68         if (*dataptr++ != 0x61) {
  69                 debug("%s: Design name identifier not recognized "
  70                         "in bitstream\n",
  71                         __func__);
  72                 return FPGA_FAIL;
  73         }
  74
  75         length = (*dataptr << 8) + *(dataptr+1);
  76         dataptr+=2;
  77         for(i=0;i<length;i++)
  78                 buffer[i] = *dataptr++;
  79
  80         printf("  design filename = \"%s\"\n", buffer);
  81
  82         /* get part number (identifier, length, string) */
  83         if (*dataptr++ != 0x62) {
  84                 printf("%s: Part number identifier not recognized "
  85                         "in bitstream\n",
  86                         __func__);
  87                 return FPGA_FAIL;
  88         }
  89
  90         length = (*dataptr << 8) + *(dataptr+1);
  91         dataptr+=2;
  92         for(i=0;i<length;i++)
  93                 buffer[i] = *dataptr++;
  94         printf("  part number = \"%s\"\n", buffer);
  95
  96         /* get date (identifier, length, string) */
  97         if (*dataptr++ != 0x63) {
  98                 printf("%s: Date identifier not recognized in bitstream\n",
  99                        __func__);
 100                 return FPGA_FAIL;
 101         }
 102
 103         length = (*dataptr << 8) + *(dataptr+1);
 104         dataptr+=2;
 105         for(i=0;i<length;i++)
 106                 buffer[i] = *dataptr++;
 107         printf("  date = \"%s\"\n", buffer);
 108
 109         /* get time (identifier, length, string) */
 110         if (*dataptr++ != 0x64) {
 111                 printf("%s: Time identifier not recognized in bitstream\n",
 112                         __func__);
 113                 return FPGA_FAIL;
 114         }
 115
 116         length = (*dataptr << 8) + *(dataptr+1);
 117         dataptr+=2;
 118         for(i=0;i<length;i++)
 119                 buffer[i] = *dataptr++;
 120         printf("  time = \"%s\"\n", buffer);
 121
 122         /* get fpga data length (identifier, length) */
 123         if (*dataptr++ != 0x65) {
 124                 printf("%s: Data length identifier not recognized in bitstream\n",
 125                         __func__);
 126                 return FPGA_FAIL;
 127         }
 128         swapsize = ((unsigned int) *dataptr     <<24) +
 129                    ((unsigned int) *(dataptr+1) <<16) +
 130                    ((unsigned int) *(dataptr+2) <<8 ) +
 131                    ((unsigned int) *(dataptr+3)     ) ;
 132         dataptr+=4;
 133         printf("  bytes in bitstream = %d\n", swapsize);
 134
 135         rc = fpga_load(dev, dataptr, swapsize);
 136         return rc;
 137 #else
 138         printf("Bitstream support only for Xilinx devices\n");
 139         return FPGA_FAIL;
 140 #endif
 141 }
 142
 143 /* ------------------------------------------------------------------------- */
 144 /* command form:
 145  *   fpga <op> <device number> <data addr> <datasize>
 146  * where op is 'load', 'dump', or 'info'
 147  * If there is no device number field, the fpga environment variable is used.
 148  * If there is no data addr field, the fpgadata environment variable is used.
 149  * The info command requires no data address field.
 150  */
 151 int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 152 {
 153         int op, dev = FPGA_INVALID_DEVICE;
 154         size_t data_size = 0;
 155         void *fpga_data = NULL;
 156         char *devstr = getenv ("fpga");
 157         char *datastr = getenv ("fpgadata");
 158         int rc = FPGA_FAIL;
 159         int wrong_parms = 0;
 160 #if defined (CONFIG_FIT)
 161         const char *fit_uname = NULL;
 162         ulong fit_addr;
 163 #endif
 164
 165         if (devstr)
 166                 dev = (int) simple_strtoul (devstr, NULL, 16);
 167         if (datastr)
 168                 fpga_data = (void *) simple_strtoul (datastr, NULL, 16);
 169
 170         switch (argc) {
 171         case 5:         /* fpga <op> <dev> <data> <datasize> */
 172                 data_size = simple_strtoul (argv[4], NULL, 16);
 173
 174         case 4:         /* fpga <op> <dev> <data> */
 175 #if defined(CONFIG_FIT)
 176                 if (fit_parse_subimage (argv[3], (ulong)fpga_data,
 177                                         &fit_addr, &fit_uname)) {
 178                         fpga_data = (void *)fit_addr;
 179                         debug("*  fpga: subimage '%s' from FIT image "
 180                                 "at 0x%08lx\n",
 181                                 fit_uname, fit_addr);
 182                 } else
 183 #endif
 184                 {
 185                         fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
 186                         debug("*  fpga: cmdline image address = 0x%08lx\n",
 187                                 (ulong)fpga_data);
 188                 }
 189                 debug("%s: fpga_data = 0x%x\n", __func__, (uint) fpga_data);
 190
 191         case 3:         /* fpga <op> <dev | data addr> */
 192                 dev = (int) simple_strtoul (argv[2], NULL, 16);
 193                 debug("%s: device = %d\n", __func__, dev);
 194                 /* FIXME - this is a really weak test */
 195                 if ((argc == 3) && (dev > fpga_count ())) {     /* must be buffer ptr */
 196                         debug("%s: Assuming buffer pointer in arg 3\n",
 197                                 __func__);
 198
 199 #if defined(CONFIG_FIT)
 200                         if (fit_parse_subimage (argv[2], (ulong)fpga_data,
 201                                                 &fit_addr, &fit_uname)) {
 202                                 fpga_data = (void *)fit_addr;
 203                                 debug("*  fpga: subimage '%s' from FIT image "
 204                                         "at 0x%08lx\n",
 205                                         fit_uname, fit_addr);
 206                         } else
 207 #endif
 208                         {
 209                                 fpga_data = (void *) dev;
 210                                 debug("*  fpga: cmdline image address = "
 211                                         "0x%08lx\n", (ulong)fpga_data);
 212                         }
 213
 214                         debug("%s: fpga_data = 0x%x\n",
 215                                 __func__, (uint) fpga_data);
 216                         dev = FPGA_INVALID_DEVICE;      /* reset device num */
 217                 }
 218
 219         case 2:         /* fpga <op> */
 220                 op = (int) fpga_get_op (argv[1]);
 221                 break;
 222
 223         default:
 224                 debug("%s: Too many or too few args (%d)\n",
 225                         __func__, argc);
 226                 op = FPGA_NONE; /* force usage display */
 227                 break;
 228         }
 229
 230         if (dev == FPGA_INVALID_DEVICE) {
 231                 puts("FPGA device not specified\n");
 232                 op = FPGA_NONE;
 233         }
 234
 235         switch (op) {
 236         case FPGA_NONE:
 237         case FPGA_INFO:
 238                 break;
 239         case FPGA_LOAD:
 240         case FPGA_LOADB:
 241         case FPGA_DUMP:
 242                 if (!fpga_data || !data_size)
 243                         wrong_parms = 1;
 244                 break;
 245         case FPGA_LOADMK:
 246                 if (!fpga_data)
 247                         wrong_parms = 1;
 248                 break;
 249         }
 250
 251         if (wrong_parms) {
 252                 puts("Wrong parameters for FPGA request\n");
 253                 op = FPGA_NONE;
 254         }
 255
 256         switch (op) {
 257         case FPGA_NONE:
 258                 return CMD_RET_USAGE;
 259
 260         case FPGA_INFO:
 261                 rc = fpga_info (dev);
 262                 break;
 263
 264         case FPGA_LOAD:
 265                 rc = fpga_load (dev, fpga_data, data_size);
 266                 break;
 267
 268         case FPGA_LOADB:
 269                 rc = fpga_loadbitstream(dev, fpga_data, data_size);
 270                 break;
 271
 272         case FPGA_LOADMK:
 273                 switch (genimg_get_format (fpga_data)) {
 274                 case IMAGE_FORMAT_LEGACY:
 275                         {
 276                                 image_header_t *hdr = (image_header_t *)fpga_data;
 277                                 ulong   data;
 278
 279                                 data = (ulong)image_get_data (hdr);
 280                                 data_size = image_get_data_size (hdr);
 281                                 rc = fpga_load (dev, (void *)data, data_size);
 282                         }
 283                         break;
 284 #if defined(CONFIG_FIT)
 285                 case IMAGE_FORMAT_FIT:
 286                         {
 287                                 const void *fit_hdr = (const void *)fpga_data;
 288                                 int noffset;
 289                                 const void *fit_data;
 290
 291                                 if (fit_uname == NULL) {
 292                                         puts ("No FIT subimage unit name\n");
 293                                         return 1;
 294                                 }
 295
 296                                 if (!fit_check_format (fit_hdr)) {
 297                                         puts ("Bad FIT image format\n");
 298                                         return 1;
 299                                 }
 300
 301                                 /* get fpga component image node offset */
 302                                 noffset = fit_image_get_node (fit_hdr, fit_uname);
 303                                 if (noffset < 0) {
 304                                         printf ("Can't find '%s' FIT subimage\n", fit_uname);
 305                                         return 1;
 306                                 }
 307
 308                                 /* verify integrity */
 309                                 if (!fit_image_check_hashes (fit_hdr, noffset)) {
 310                                         puts ("Bad Data Hash\n");
 311                                         return 1;
 312                                 }
 313
 314                                 /* get fpga subimage data address and length */
 315                                 if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) {
 316                                         puts ("Could not find fpga subimage data\n");
 317                                         return 1;
 318                                 }
 319
 320                                 rc = fpga_load (dev, fit_data, data_size);
 321                         }
 322                         break;
 323 #endif
 324                 default:
 325                         puts ("** Unknown image type\n");
 326                         rc = FPGA_FAIL;
 327                         break;
 328                 }
 329                 break;
 330
 331         case FPGA_DUMP:
 332                 rc = fpga_dump (dev, fpga_data, data_size);
 333                 break;
 334
 335         default:
 336                 printf ("Unknown operation\n");
 337                 return CMD_RET_USAGE;
 338         }
 339         return (rc);
 340 }
 341
 342 /*
 343  * Map op to supported operations.  We don't use a table since we
 344  * would just have to relocate it from flash anyway.
 345  */
 346 static int fpga_get_op (char *opstr)
 347 {
 348         int op = FPGA_NONE;
 349
 350         if (!strcmp ("info", opstr)) {
 351                 op = FPGA_INFO;
 352         } else if (!strcmp ("loadb", opstr)) {
 353                 op = FPGA_LOADB;
 354         } else if (!strcmp ("load", opstr)) {
 355                 op = FPGA_LOAD;
 356         } else if (!strcmp ("loadmk", opstr)) {
 357                 op = FPGA_LOADMK;
 358         } else if (!strcmp ("dump", opstr)) {
 359                 op = FPGA_DUMP;
 360         }
 361
 362         if (op == FPGA_NONE) {
 363                 printf ("Unknown fpga operation \"%s\"\n", opstr);
 364         }
 365         return op;
 366 }
 367
 368 U_BOOT_CMD (fpga, 6, 1, do_fpga,
 369         "loadable FPGA image support",
 370         "[operation type] [device number] [image address] [image size]\n"
 371         "fpga operations:\n"
 372         "  dump\t[dev]\t\t\tLoad device to memory buffer\n"
 373         "  info\t[dev]\t\t\tlist known device information\n"
 374         "  load\t[dev] [address] [size]\tLoad device from memory buffer\n"
 375         "  loadb\t[dev] [address] [size]\t"
 376         "Load device from bitstream buffer (Xilinx only)\n"
 377         "  loadmk [dev] [address]\tLoad device generated with mkimage"
 378 #if defined(CONFIG_FIT)
 379         "\n"
 380         "\tFor loadmk operating on FIT format uImage address must include\n"
 381         "\tsubimage unit name in the form of addr:<subimg_uname>"
 382 #endif
 383 );