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1 /*
2 * (C) Copyright 2000, 2001
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25 /*
26 * FPGA support
27 */
28 #include <common.h>
29 #include <command.h>
30 #if defined(CONFIG_CMD_NET)
31 #include <net.h>
32 #endif
33 #include <fpga.h>
34 #include <malloc.h>
35
36 #if 0
37 #define FPGA_DEBUG
38 #endif
39
40 #ifdef FPGA_DEBUG
41 #define PRINTF(fmt,args...) printf (fmt ,##args)
42 #else
43 #define PRINTF(fmt,args...)
44 #endif
45
46 /* Local functions */
47 static int fpga_get_op (char *opstr);
48
49 /* Local defines */
50 #define FPGA_NONE -1
51 #define FPGA_INFO 0
52 #define FPGA_LOAD 1
53 #define FPGA_LOADB 2
54 #define FPGA_DUMP 3
55 #define FPGA_LOADMK 4
56
57 /* Convert bitstream data and load into the fpga */
58 int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
59 {
60 #if defined(CONFIG_FPGA_XILINX)
61 unsigned int length;
62 unsigned int swapsize;
63 char buffer[80];
64 unsigned char *dataptr;
65 unsigned int i;
66 int rc;
67
68 dataptr = (unsigned char *)fpgadata;
69
70 /* skip the first bytes of the bitsteam, their meaning is unknown */
71 length = (*dataptr << 8) + *(dataptr+1);
72 dataptr+=2;
73 dataptr+=length;
74
75 /* get design name (identifier, length, string) */
76 length = (*dataptr << 8) + *(dataptr+1);
77 dataptr+=2;
78 if (*dataptr++ != 0x61) {
79 PRINTF ("%s: Design name identifier not recognized in bitstream\n",
80 __FUNCTION__ );
81 return FPGA_FAIL;
82 }
83
84 length = (*dataptr << 8) + *(dataptr+1);
85 dataptr+=2;
86 for(i=0;i<length;i++)
87 buffer[i] = *dataptr++;
88
89 printf(" design filename = \"%s\"\n", buffer);
90
91 /* get part number (identifier, length, string) */
92 if (*dataptr++ != 0x62) {
93 printf("%s: Part number identifier not recognized in bitstream\n",
94 __FUNCTION__ );
95 return FPGA_FAIL;
96 }
97
98 length = (*dataptr << 8) + *(dataptr+1);
99 dataptr+=2;
100 for(i=0;i<length;i++)
101 buffer[i] = *dataptr++;
102 printf(" part number = \"%s\"\n", buffer);
103
104 /* get date (identifier, length, string) */
105 if (*dataptr++ != 0x63) {
106 printf("%s: Date identifier not recognized in bitstream\n",
107 __FUNCTION__);
108 return FPGA_FAIL;
109 }
110
111 length = (*dataptr << 8) + *(dataptr+1);
112 dataptr+=2;
113 for(i=0;i<length;i++)
114 buffer[i] = *dataptr++;
115 printf(" date = \"%s\"\n", buffer);
116
117 /* get time (identifier, length, string) */
118 if (*dataptr++ != 0x64) {
119 printf("%s: Time identifier not recognized in bitstream\n",__FUNCTION__);
120 return FPGA_FAIL;
121 }
122
123 length = (*dataptr << 8) + *(dataptr+1);
124 dataptr+=2;
125 for(i=0;i<length;i++)
126 buffer[i] = *dataptr++;
127 printf(" time = \"%s\"\n", buffer);
128
129 /* get fpga data length (identifier, length) */
130 if (*dataptr++ != 0x65) {
131 printf("%s: Data length identifier not recognized in bitstream\n",
132 __FUNCTION__);
133 return FPGA_FAIL;
134 }
135 swapsize = ((unsigned int) *dataptr <<24) +
136 ((unsigned int) *(dataptr+1) <<16) +
137 ((unsigned int) *(dataptr+2) <<8 ) +
138 ((unsigned int) *(dataptr+3) ) ;
139 dataptr+=4;
140 printf(" bytes in bitstream = %d\n", swapsize);
141
142 rc = fpga_load(dev, dataptr, swapsize);
143 return rc;
144 #else
145 printf("Bitstream support only for Xilinx devices\n");
146 return FPGA_FAIL;
147 #endif
148 }
149
150 /* ------------------------------------------------------------------------- */
151 /* command form:
152 * fpga <op> <device number> <data addr> <datasize>
153 * where op is 'load', 'dump', or 'info'
154 * If there is no device number field, the fpga environment variable is used.
155 * If there is no data addr field, the fpgadata environment variable is used.
156 * The info command requires no data address field.
157 */
158 int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
159 {
160 int op, dev = FPGA_INVALID_DEVICE;
161 size_t data_size = 0;
162 void *fpga_data = NULL;
163 char *devstr = getenv ("fpga");
164 char *datastr = getenv ("fpgadata");
165 int rc = FPGA_FAIL;
166 #if defined (CONFIG_FIT)
167 const char *fit_uname = NULL;
168 ulong fit_addr;
169 #endif
170
171 if (devstr)
172 dev = (int) simple_strtoul (devstr, NULL, 16);
173 if (datastr)
174 fpga_data = (void *) simple_strtoul (datastr, NULL, 16);
175
176 switch (argc) {
177 case 5: /* fpga <op> <dev> <data> <datasize> */
178 data_size = simple_strtoul (argv[4], NULL, 16);
179
180 case 4: /* fpga <op> <dev> <data> */
181 #if defined(CONFIG_FIT)
182 if (fit_parse_subimage (argv[3], (ulong)fpga_data,
183 &fit_addr, &fit_uname)) {
184 fpga_data = (void *)fit_addr;
185 debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n",
186 fit_uname, fit_addr);
187 } else
188 #endif
189 {
190 fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
191 debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
192 }
193 PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data);
194
195 case 3: /* fpga <op> <dev | data addr> */
196 dev = (int) simple_strtoul (argv[2], NULL, 16);
197 PRINTF ("%s: device = %d\n", __FUNCTION__, dev);
198 /* FIXME - this is a really weak test */
199 if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */
200 PRINTF ("%s: Assuming buffer pointer in arg 3\n",
201 __FUNCTION__);
202
203 #if defined(CONFIG_FIT)
204 if (fit_parse_subimage (argv[2], (ulong)fpga_data,
205 &fit_addr, &fit_uname)) {
206 fpga_data = (void *)fit_addr;
207 debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n",
208 fit_uname, fit_addr);
209 } else
210 #endif
211 {
212 fpga_data = (void *) dev;
213 debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
214 }
215
216 PRINTF ("%s: fpga_data = 0x%x\n",
217 __FUNCTION__, (uint) fpga_data);
218 dev = FPGA_INVALID_DEVICE; /* reset device num */
219 }
220
221 case 2: /* fpga <op> */
222 op = (int) fpga_get_op (argv[1]);
223 break;
224
225 default:
226 PRINTF ("%s: Too many or too few args (%d)\n",
227 __FUNCTION__, argc);
228 op = FPGA_NONE; /* force usage display */
229 break;
230 }
231
232 switch (op) {
233 case FPGA_NONE:
234 return cmd_usage(cmdtp);
235
236 case FPGA_INFO:
237 rc = fpga_info (dev);
238 break;
239
240 case FPGA_LOAD:
241 rc = fpga_load (dev, fpga_data, data_size);
242 break;
243
244 case FPGA_LOADB:
245 rc = fpga_loadbitstream(dev, fpga_data, data_size);
246 break;
247
248 case FPGA_LOADMK:
249 switch (genimg_get_format (fpga_data)) {
250 case IMAGE_FORMAT_LEGACY:
251 {
252 image_header_t *hdr = (image_header_t *)fpga_data;
253 ulong data;
254
255 data = (ulong)image_get_data (hdr);
256 data_size = image_get_data_size (hdr);
257 rc = fpga_load (dev, (void *)data, data_size);
258 }
259 break;
260 #if defined(CONFIG_FIT)
261 case IMAGE_FORMAT_FIT:
262 {
263 const void *fit_hdr = (const void *)fpga_data;
264 int noffset;
265 void *fit_data;
266
267 if (fit_uname == NULL) {
268 puts ("No FIT subimage unit name\n");
269 return 1;
270 }
271
272 if (!fit_check_format (fit_hdr)) {
273 puts ("Bad FIT image format\n");
274 return 1;
275 }
276
277 /* get fpga component image node offset */
278 noffset = fit_image_get_node (fit_hdr, fit_uname);
279 if (noffset < 0) {
280 printf ("Can't find '%s' FIT subimage\n", fit_uname);
281 return 1;
282 }
283
284 /* verify integrity */
285 if (!fit_image_check_hashes (fit_hdr, noffset)) {
286 puts ("Bad Data Hash\n");
287 return 1;
288 }
289
290 /* get fpga subimage data address and length */
291 if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) {
292 puts ("Could not find fpga subimage data\n");
293 return 1;
294 }
295
296 rc = fpga_load (dev, fit_data, data_size);
297 }
298 break;
299 #endif
300 default:
301 puts ("** Unknown image type\n");
302 rc = FPGA_FAIL;
303 break;
304 }
305 break;
306
307 case FPGA_DUMP:
308 rc = fpga_dump (dev, fpga_data, data_size);
309 break;
310
311 default:
312 printf ("Unknown operation\n");
313 return cmd_usage(cmdtp);
314 }
315 return (rc);
316 }
317
318 /*
319 * Map op to supported operations. We don't use a table since we
320 * would just have to relocate it from flash anyway.
321 */
322 static int fpga_get_op (char *opstr)
323 {
324 int op = FPGA_NONE;
325
326 if (!strcmp ("info", opstr)) {
327 op = FPGA_INFO;
328 } else if (!strcmp ("loadb", opstr)) {
329 op = FPGA_LOADB;
330 } else if (!strcmp ("load", opstr)) {
331 op = FPGA_LOAD;
332 } else if (!strcmp ("loadmk", opstr)) {
333 op = FPGA_LOADMK;
334 } else if (!strcmp ("dump", opstr)) {
335 op = FPGA_DUMP;
336 }
337
338 if (op == FPGA_NONE) {
339 printf ("Unknown fpga operation \"%s\"\n", opstr);
340 }
341 return op;
342 }
343
344 U_BOOT_CMD (fpga, 6, 1, do_fpga,
345 "loadable FPGA image support",
346 "fpga [operation type] [device number] [image address] [image size]\n"
347 "fpga operations:\n"
348 "\tinfo\tlist known device information\n"
349 "\tload\tLoad device from memory buffer\n"
350 "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n"
351 "\tloadmk\tLoad device generated with mkimage\n"
352 "\tdump\tLoad device to memory buffer"
353 #if defined(CONFIG_FIT)
354 "\n"
355 "\tFor loadmk operating on FIT format uImage address must include\n"
356 "\tsubimage unit name in the form of addr:<subimg_uname>"
357 #endif
358 );