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1 /*
2 * (C) Copyright 2001
3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 * I2C Functions similar to the standard memory functions.
26 *
27 * There are several parameters in many of the commands that bear further
28 * explanations:
29 *
30 * {i2c_chip} is the I2C chip address (the first byte sent on the bus).
31 * Each I2C chip on the bus has a unique address. On the I2C data bus,
32 * the address is the upper seven bits and the LSB is the "read/write"
33 * bit. Note that the {i2c_chip} address specified on the command
34 * line is not shifted up: e.g. a typical EEPROM memory chip may have
35 * an I2C address of 0x50, but the data put on the bus will be 0xA0
36 * for write and 0xA1 for read. This "non shifted" address notation
37 * matches at least half of the data sheets :-/.
38 *
39 * {addr} is the address (or offset) within the chip. Small memory
40 * chips have 8 bit addresses. Large memory chips have 16 bit
41 * addresses. Other memory chips have 9, 10, or 11 bit addresses.
42 * Many non-memory chips have multiple registers and {addr} is used
43 * as the register index. Some non-memory chips have only one register
44 * and therefore don't need any {addr} parameter.
45 *
46 * The default {addr} parameter is one byte (.1) which works well for
47 * memories and registers with 8 bits of address space.
48 *
49 * You can specify the length of the {addr} field with the optional .0,
50 * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are
51 * manipulating a single register device which doesn't use an address
52 * field, use "0.0" for the address and the ".0" length field will
53 * suppress the address in the I2C data stream. This also works for
54 * successive reads using the I2C auto-incrementing memory pointer.
55 *
56 * If you are manipulating a large memory with 2-byte addresses, use
57 * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal).
58 *
59 * Then there are the unfortunate memory chips that spill the most
60 * significant 1, 2, or 3 bits of address into the chip address byte.
61 * This effectively makes one chip (logically) look like 2, 4, or
62 * 8 chips. This is handled (awkwardly) by #defining
63 * CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
64 * {addr} field (since .1 is the default, it doesn't actually have to
65 * be specified). Examples: given a memory chip at I2C chip address
66 * 0x50, the following would happen...
67 * i2c md 50 0 10 display 16 bytes starting at 0x000
68 * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
69 * i2c md 50 100 10 display 16 bytes starting at 0x100
70 * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
71 * i2c md 50 210 10 display 16 bytes starting at 0x210
72 * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
73 * This is awfully ugly. It would be nice if someone would think up
74 * a better way of handling this.
75 *
76 * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de).
77 */
78
79 #include <common.h>
80 #include <command.h>
81 #include <environment.h>
82 #include <i2c.h>
83 #include <malloc.h>
84 #include <asm/byteorder.h>
85
86 /* Display values from last command.
87 * Memory modify remembered values are different from display memory.
88 */
89 static uchar i2c_dp_last_chip;
90 static uint i2c_dp_last_addr;
91 static uint i2c_dp_last_alen;
92 static uint i2c_dp_last_length = 0x10;
93
94 static uchar i2c_mm_last_chip;
95 static uint i2c_mm_last_addr;
96 static uint i2c_mm_last_alen;
97
98 /* If only one I2C bus is present, the list of devices to ignore when
99 * the probe command is issued is represented by a 1D array of addresses.
100 * When multiple buses are present, the list is an array of bus-address
101 * pairs. The following macros take care of this */
102
103 #if defined(CONFIG_SYS_I2C_NOPROBES)
104 #if defined(CONFIG_I2C_MULTI_BUS)
105 static struct
106 {
107 uchar bus;
108 uchar addr;
109 } i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
110 #define GET_BUS_NUM i2c_get_bus_num()
111 #define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
112 #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
113 #define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
114 #else /* single bus */
115 static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
116 #define GET_BUS_NUM 0
117 #define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
118 #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
119 #define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
120 #endif /* CONFIG_MULTI_BUS */
121
122 #define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0]))
123 #endif
124
125 #if defined(CONFIG_I2C_MUX)
126 static I2C_MUX_DEVICE *i2c_mux_devices = NULL;
127 static int i2c_mux_busid = CONFIG_SYS_MAX_I2C_BUS;
128
129 DECLARE_GLOBAL_DATA_PTR;
130
131 #endif
132
133 #define DISP_LINE_LEN 16
134
135 /* TODO: Implement architecture-specific get/set functions */
136 unsigned int __def_i2c_get_bus_speed(void)
137 {
138 return CONFIG_SYS_I2C_SPEED;
139 }
140 unsigned int i2c_get_bus_speed(void)
141 __attribute__((weak, alias("__def_i2c_get_bus_speed")));
142
143 int __def_i2c_set_bus_speed(unsigned int speed)
144 {
145 if (speed != CONFIG_SYS_I2C_SPEED)
146 return -1;
147
148 return 0;
149 }
150 int i2c_set_bus_speed(unsigned int)
151 __attribute__((weak, alias("__def_i2c_set_bus_speed")));
152
153 /*
154 * get_alen: small parser helper function to get address length
155 * returns the address length,or 0 on error
156 */
157 static uint get_alen(char *arg)
158 {
159 int j;
160 int alen;
161
162 alen = 1;
163 for (j = 0; j < 8; j++) {
164 if (arg[j] == '.') {
165 alen = arg[j+1] - '0';
166 if (alen > 3) {
167 return 0;
168 }
169 break;
170 } else if (arg[j] == '\0')
171 break;
172 }
173 return alen;
174 }
175
176 /*
177 * Syntax:
178 * i2c read {i2c_chip} {devaddr}{.0, .1, .2} {len} {memaddr}
179 */
180
181 static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
182 {
183 u_char chip;
184 uint devaddr, alen, length;
185 u_char *memaddr;
186
187 if (argc != 5) {
188 cmd_usage(cmdtp);
189 return 1;
190 }
191
192 /*
193 * I2C chip address
194 */
195 chip = simple_strtoul(argv[1], NULL, 16);
196
197 /*
198 * I2C data address within the chip. This can be 1 or
199 * 2 bytes long. Some day it might be 3 bytes long :-).
200 */
201 devaddr = simple_strtoul(argv[2], NULL, 16);
202 alen = get_alen(argv[2]);
203 if (alen == 0) {
204 cmd_usage(cmdtp);
205 return 1;
206 }
207
208 /*
209 * Length is the number of objects, not number of bytes.
210 */
211 length = simple_strtoul(argv[3], NULL, 16);
212
213 /*
214 * memaddr is the address where to store things in memory
215 */
216 memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
217
218 if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) {
219 puts ("Error reading the chip.\n");
220 return 1;
221 }
222 return 0;
223 }
224
225 /*
226 * Syntax:
227 * i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
228 */
229 static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
230 {
231 u_char chip;
232 uint addr, alen, length;
233 int j, nbytes, linebytes;
234
235 /* We use the last specified parameters, unless new ones are
236 * entered.
237 */
238 chip = i2c_dp_last_chip;
239 addr = i2c_dp_last_addr;
240 alen = i2c_dp_last_alen;
241 length = i2c_dp_last_length;
242
243 if (argc < 3) {
244 cmd_usage(cmdtp);
245 return 1;
246 }
247
248 if ((flag & CMD_FLAG_REPEAT) == 0) {
249 /*
250 * New command specified.
251 */
252
253 /*
254 * I2C chip address
255 */
256 chip = simple_strtoul(argv[1], NULL, 16);
257
258 /*
259 * I2C data address within the chip. This can be 1 or
260 * 2 bytes long. Some day it might be 3 bytes long :-).
261 */
262 addr = simple_strtoul(argv[2], NULL, 16);
263 alen = get_alen(argv[2]);
264 if (alen == 0) {
265 cmd_usage(cmdtp);
266 return 1;
267 }
268
269 /*
270 * If another parameter, it is the length to display.
271 * Length is the number of objects, not number of bytes.
272 */
273 if (argc > 3)
274 length = simple_strtoul(argv[3], NULL, 16);
275 }
276
277 /*
278 * Print the lines.
279 *
280 * We buffer all read data, so we can make sure data is read only
281 * once.
282 */
283 nbytes = length;
284 do {
285 unsigned char linebuf[DISP_LINE_LEN];
286 unsigned char *cp;
287
288 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
289
290 if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
291 puts ("Error reading the chip.\n");
292 else {
293 printf("%04x:", addr);
294 cp = linebuf;
295 for (j=0; j<linebytes; j++) {
296 printf(" %02x", *cp++);
297 addr++;
298 }
299 puts (" ");
300 cp = linebuf;
301 for (j=0; j<linebytes; j++) {
302 if ((*cp < 0x20) || (*cp > 0x7e))
303 puts (".");
304 else
305 printf("%c", *cp);
306 cp++;
307 }
308 putc ('\n');
309 }
310 nbytes -= linebytes;
311 } while (nbytes > 0);
312
313 i2c_dp_last_chip = chip;
314 i2c_dp_last_addr = addr;
315 i2c_dp_last_alen = alen;
316 i2c_dp_last_length = length;
317
318 return 0;
319 }
320
321
322 /* Write (fill) memory
323 *
324 * Syntax:
325 * i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
326 */
327 static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
328 {
329 uchar chip;
330 ulong addr;
331 uint alen;
332 uchar byte;
333 int count;
334
335 if ((argc < 4) || (argc > 5)) {
336 cmd_usage(cmdtp);
337 return 1;
338 }
339
340 /*
341 * Chip is always specified.
342 */
343 chip = simple_strtoul(argv[1], NULL, 16);
344
345 /*
346 * Address is always specified.
347 */
348 addr = simple_strtoul(argv[2], NULL, 16);
349 alen = get_alen(argv[2]);
350 if (alen == 0) {
351 cmd_usage(cmdtp);
352 return 1;
353 }
354
355 /*
356 * Value to write is always specified.
357 */
358 byte = simple_strtoul(argv[3], NULL, 16);
359
360 /*
361 * Optional count
362 */
363 if (argc == 5)
364 count = simple_strtoul(argv[4], NULL, 16);
365 else
366 count = 1;
367
368 while (count-- > 0) {
369 if (i2c_write(chip, addr++, alen, &byte, 1) != 0)
370 puts ("Error writing the chip.\n");
371 /*
372 * Wait for the write to complete. The write can take
373 * up to 10mSec (we allow a little more time).
374 */
375 /*
376 * No write delay with FRAM devices.
377 */
378 #if !defined(CONFIG_SYS_I2C_FRAM)
379 udelay(11000);
380 #endif
381 }
382
383 return (0);
384 }
385
386 /* Calculate a CRC on memory
387 *
388 * Syntax:
389 * i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count}
390 */
391 static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
392 {
393 uchar chip;
394 ulong addr;
395 uint alen;
396 int count;
397 uchar byte;
398 ulong crc;
399 ulong err;
400
401 if (argc < 4) {
402 cmd_usage(cmdtp);
403 return 1;
404 }
405
406 /*
407 * Chip is always specified.
408 */
409 chip = simple_strtoul(argv[1], NULL, 16);
410
411 /*
412 * Address is always specified.
413 */
414 addr = simple_strtoul(argv[2], NULL, 16);
415 alen = get_alen(argv[2]);
416 if (alen == 0) {
417 cmd_usage(cmdtp);
418 return 1;
419 }
420
421 /*
422 * Count is always specified
423 */
424 count = simple_strtoul(argv[3], NULL, 16);
425
426 printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
427 /*
428 * CRC a byte at a time. This is going to be slooow, but hey, the
429 * memories are small and slow too so hopefully nobody notices.
430 */
431 crc = 0;
432 err = 0;
433 while (count-- > 0) {
434 if (i2c_read(chip, addr, alen, &byte, 1) != 0)
435 err++;
436 crc = crc32 (crc, &byte, 1);
437 addr++;
438 }
439 if (err > 0)
440 puts ("Error reading the chip,\n");
441 else
442 printf ("%08lx\n", crc);
443
444 return 0;
445 }
446
447 /* Modify memory.
448 *
449 * Syntax:
450 * i2c mm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
451 * i2c nm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
452 */
453
454 static int
455 mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
456 {
457 uchar chip;
458 ulong addr;
459 uint alen;
460 ulong data;
461 int size = 1;
462 int nbytes;
463 extern char console_buffer[];
464
465 if (argc != 3) {
466 cmd_usage(cmdtp);
467 return 1;
468 }
469
470 #ifdef CONFIG_BOOT_RETRY_TIME
471 reset_cmd_timeout(); /* got a good command to get here */
472 #endif
473 /*
474 * We use the last specified parameters, unless new ones are
475 * entered.
476 */
477 chip = i2c_mm_last_chip;
478 addr = i2c_mm_last_addr;
479 alen = i2c_mm_last_alen;
480
481 if ((flag & CMD_FLAG_REPEAT) == 0) {
482 /*
483 * New command specified. Check for a size specification.
484 * Defaults to byte if no or incorrect specification.
485 */
486 size = cmd_get_data_size(argv[0], 1);
487
488 /*
489 * Chip is always specified.
490 */
491 chip = simple_strtoul(argv[1], NULL, 16);
492
493 /*
494 * Address is always specified.
495 */
496 addr = simple_strtoul(argv[2], NULL, 16);
497 alen = get_alen(argv[2]);
498 if (alen == 0) {
499 cmd_usage(cmdtp);
500 return 1;
501 }
502 }
503
504 /*
505 * Print the address, followed by value. Then accept input for
506 * the next value. A non-converted value exits.
507 */
508 do {
509 printf("%08lx:", addr);
510 if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0)
511 puts ("\nError reading the chip,\n");
512 else {
513 data = cpu_to_be32(data);
514 if (size == 1)
515 printf(" %02lx", (data >> 24) & 0x000000FF);
516 else if (size == 2)
517 printf(" %04lx", (data >> 16) & 0x0000FFFF);
518 else
519 printf(" %08lx", data);
520 }
521
522 nbytes = readline (" ? ");
523 if (nbytes == 0) {
524 /*
525 * <CR> pressed as only input, don't modify current
526 * location and move to next.
527 */
528 if (incrflag)
529 addr += size;
530 nbytes = size;
531 #ifdef CONFIG_BOOT_RETRY_TIME
532 reset_cmd_timeout(); /* good enough to not time out */
533 #endif
534 }
535 #ifdef CONFIG_BOOT_RETRY_TIME
536 else if (nbytes == -2)
537 break; /* timed out, exit the command */
538 #endif
539 else {
540 char *endp;
541
542 data = simple_strtoul(console_buffer, &endp, 16);
543 if (size == 1)
544 data = data << 24;
545 else if (size == 2)
546 data = data << 16;
547 data = be32_to_cpu(data);
548 nbytes = endp - console_buffer;
549 if (nbytes) {
550 #ifdef CONFIG_BOOT_RETRY_TIME
551 /*
552 * good enough to not time out
553 */
554 reset_cmd_timeout();
555 #endif
556 if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
557 puts ("Error writing the chip.\n");
558 #ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
559 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
560 #endif
561 if (incrflag)
562 addr += size;
563 }
564 }
565 } while (nbytes);
566
567 i2c_mm_last_chip = chip;
568 i2c_mm_last_addr = addr;
569 i2c_mm_last_alen = alen;
570
571 return 0;
572 }
573
574 /*
575 * Syntax:
576 * i2c probe {addr}{.0, .1, .2}
577 */
578 static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
579 {
580 int j;
581 #if defined(CONFIG_SYS_I2C_NOPROBES)
582 int k, skip;
583 uchar bus = GET_BUS_NUM;
584 #endif /* NOPROBES */
585
586 puts ("Valid chip addresses:");
587 for (j = 0; j < 128; j++) {
588 #if defined(CONFIG_SYS_I2C_NOPROBES)
589 skip = 0;
590 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
591 if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
592 skip = 1;
593 break;
594 }
595 }
596 if (skip)
597 continue;
598 #endif
599 if (i2c_probe(j) == 0)
600 printf(" %02X", j);
601 }
602 putc ('\n');
603
604 #if defined(CONFIG_SYS_I2C_NOPROBES)
605 puts ("Excluded chip addresses:");
606 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
607 if (COMPARE_BUS(bus,k))
608 printf(" %02X", NO_PROBE_ADDR(k));
609 }
610 putc ('\n');
611 #endif
612
613 return 0;
614 }
615
616 /*
617 * Syntax:
618 * i2c loop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
619 * {length} - Number of bytes to read
620 * {delay} - A DECIMAL number and defaults to 1000 uSec
621 */
622 static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
623 {
624 u_char chip;
625 ulong alen;
626 uint addr;
627 uint length;
628 u_char bytes[16];
629 int delay;
630
631 if (argc < 3) {
632 cmd_usage(cmdtp);
633 return 1;
634 }
635
636 /*
637 * Chip is always specified.
638 */
639 chip = simple_strtoul(argv[1], NULL, 16);
640
641 /*
642 * Address is always specified.
643 */
644 addr = simple_strtoul(argv[2], NULL, 16);
645 alen = get_alen(argv[2]);
646 if (alen == 0) {
647 cmd_usage(cmdtp);
648 return 1;
649 }
650
651 /*
652 * Length is the number of objects, not number of bytes.
653 */
654 length = 1;
655 length = simple_strtoul(argv[3], NULL, 16);
656 if (length > sizeof(bytes))
657 length = sizeof(bytes);
658
659 /*
660 * The delay time (uSec) is optional.
661 */
662 delay = 1000;
663 if (argc > 3)
664 delay = simple_strtoul(argv[4], NULL, 10);
665 /*
666 * Run the loop...
667 */
668 while (1) {
669 if (i2c_read(chip, addr, alen, bytes, length) != 0)
670 puts ("Error reading the chip.\n");
671 udelay(delay);
672 }
673
674 /* NOTREACHED */
675 return 0;
676 }
677
678 /*
679 * The SDRAM command is separately configured because many
680 * (most?) embedded boards don't use SDRAM DIMMs.
681 */
682 #if defined(CONFIG_CMD_SDRAM)
683 static void print_ddr2_tcyc (u_char const b)
684 {
685 printf ("%d.", (b >> 4) & 0x0F);
686 switch (b & 0x0F) {
687 case 0x0:
688 case 0x1:
689 case 0x2:
690 case 0x3:
691 case 0x4:
692 case 0x5:
693 case 0x6:
694 case 0x7:
695 case 0x8:
696 case 0x9:
697 printf ("%d ns\n", b & 0x0F);
698 break;
699 case 0xA:
700 puts ("25 ns\n");
701 break;
702 case 0xB:
703 puts ("33 ns\n");
704 break;
705 case 0xC:
706 puts ("66 ns\n");
707 break;
708 case 0xD:
709 puts ("75 ns\n");
710 break;
711 default:
712 puts ("?? ns\n");
713 break;
714 }
715 }
716
717 static void decode_bits (u_char const b, char const *str[], int const do_once)
718 {
719 u_char mask;
720
721 for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
722 if (b & mask) {
723 puts (*str);
724 if (do_once)
725 return;
726 }
727 }
728 }
729
730 /*
731 * Syntax:
732 * i2c sdram {i2c_chip}
733 */
734 static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
735 {
736 enum { unknown, EDO, SDRAM, DDR2 } type;
737
738 u_char chip;
739 u_char data[128];
740 u_char cksum;
741 int j;
742
743 static const char *decode_CAS_DDR2[] = {
744 " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
745 };
746
747 static const char *decode_CAS_default[] = {
748 " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
749 };
750
751 static const char *decode_CS_WE_default[] = {
752 " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
753 };
754
755 static const char *decode_byte21_default[] = {
756 " TBD (bit 7)\n",
757 " Redundant row address\n",
758 " Differential clock input\n",
759 " Registerd DQMB inputs\n",
760 " Buffered DQMB inputs\n",
761 " On-card PLL\n",
762 " Registered address/control lines\n",
763 " Buffered address/control lines\n"
764 };
765
766 static const char *decode_byte22_DDR2[] = {
767 " TBD (bit 7)\n",
768 " TBD (bit 6)\n",
769 " TBD (bit 5)\n",
770 " TBD (bit 4)\n",
771 " TBD (bit 3)\n",
772 " Supports partial array self refresh\n",
773 " Supports 50 ohm ODT\n",
774 " Supports weak driver\n"
775 };
776
777 static const char *decode_row_density_DDR2[] = {
778 "512 MiB", "256 MiB", "128 MiB", "16 GiB",
779 "8 GiB", "4 GiB", "2 GiB", "1 GiB"
780 };
781
782 static const char *decode_row_density_default[] = {
783 "512 MiB", "256 MiB", "128 MiB", "64 MiB",
784 "32 MiB", "16 MiB", "8 MiB", "4 MiB"
785 };
786
787 if (argc < 2) {
788 cmd_usage(cmdtp);
789 return 1;
790 }
791 /*
792 * Chip is always specified.
793 */
794 chip = simple_strtoul (argv[1], NULL, 16);
795
796 if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
797 puts ("No SDRAM Serial Presence Detect found.\n");
798 return 1;
799 }
800
801 cksum = 0;
802 for (j = 0; j < 63; j++) {
803 cksum += data[j];
804 }
805 if (cksum != data[63]) {
806 printf ("WARNING: Configuration data checksum failure:\n"
807 " is 0x%02x, calculated 0x%02x\n", data[63], cksum);
808 }
809 printf ("SPD data revision %d.%d\n",
810 (data[62] >> 4) & 0x0F, data[62] & 0x0F);
811 printf ("Bytes used 0x%02X\n", data[0]);
812 printf ("Serial memory size 0x%02X\n", 1 << data[1]);
813
814 puts ("Memory type ");
815 switch (data[2]) {
816 case 2:
817 type = EDO;
818 puts ("EDO\n");
819 break;
820 case 4:
821 type = SDRAM;
822 puts ("SDRAM\n");
823 break;
824 case 8:
825 type = DDR2;
826 puts ("DDR2\n");
827 break;
828 default:
829 type = unknown;
830 puts ("unknown\n");
831 break;
832 }
833
834 puts ("Row address bits ");
835 if ((data[3] & 0x00F0) == 0)
836 printf ("%d\n", data[3] & 0x0F);
837 else
838 printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
839
840 puts ("Column address bits ");
841 if ((data[4] & 0x00F0) == 0)
842 printf ("%d\n", data[4] & 0x0F);
843 else
844 printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
845
846 switch (type) {
847 case DDR2:
848 printf ("Number of ranks %d\n",
849 (data[5] & 0x07) + 1);
850 break;
851 default:
852 printf ("Module rows %d\n", data[5]);
853 break;
854 }
855
856 switch (type) {
857 case DDR2:
858 printf ("Module data width %d bits\n", data[6]);
859 break;
860 default:
861 printf ("Module data width %d bits\n",
862 (data[7] << 8) | data[6]);
863 break;
864 }
865
866 puts ("Interface signal levels ");
867 switch(data[8]) {
868 case 0: puts ("TTL 5.0 V\n"); break;
869 case 1: puts ("LVTTL\n"); break;
870 case 2: puts ("HSTL 1.5 V\n"); break;
871 case 3: puts ("SSTL 3.3 V\n"); break;
872 case 4: puts ("SSTL 2.5 V\n"); break;
873 case 5: puts ("SSTL 1.8 V\n"); break;
874 default: puts ("unknown\n"); break;
875 }
876
877 switch (type) {
878 case DDR2:
879 printf ("SDRAM cycle time ");
880 print_ddr2_tcyc (data[9]);
881 break;
882 default:
883 printf ("SDRAM cycle time %d.%d ns\n",
884 (data[9] >> 4) & 0x0F, data[9] & 0x0F);
885 break;
886 }
887
888 switch (type) {
889 case DDR2:
890 printf ("SDRAM access time 0.%d%d ns\n",
891 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
892 break;
893 default:
894 printf ("SDRAM access time %d.%d ns\n",
895 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
896 break;
897 }
898
899 puts ("EDC configuration ");
900 switch (data[11]) {
901 case 0: puts ("None\n"); break;
902 case 1: puts ("Parity\n"); break;
903 case 2: puts ("ECC\n"); break;
904 default: puts ("unknown\n"); break;
905 }
906
907 if ((data[12] & 0x80) == 0)
908 puts ("No self refresh, rate ");
909 else
910 puts ("Self refresh, rate ");
911
912 switch(data[12] & 0x7F) {
913 case 0: puts ("15.625 us\n"); break;
914 case 1: puts ("3.9 us\n"); break;
915 case 2: puts ("7.8 us\n"); break;
916 case 3: puts ("31.3 us\n"); break;
917 case 4: puts ("62.5 us\n"); break;
918 case 5: puts ("125 us\n"); break;
919 default: puts ("unknown\n"); break;
920 }
921
922 switch (type) {
923 case DDR2:
924 printf ("SDRAM width (primary) %d\n", data[13]);
925 break;
926 default:
927 printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
928 if ((data[13] & 0x80) != 0) {
929 printf (" (second bank) %d\n",
930 2 * (data[13] & 0x7F));
931 }
932 break;
933 }
934
935 switch (type) {
936 case DDR2:
937 if (data[14] != 0)
938 printf ("EDC width %d\n", data[14]);
939 break;
940 default:
941 if (data[14] != 0) {
942 printf ("EDC width %d\n",
943 data[14] & 0x7F);
944
945 if ((data[14] & 0x80) != 0) {
946 printf (" (second bank) %d\n",
947 2 * (data[14] & 0x7F));
948 }
949 }
950 break;
951 }
952
953 if (DDR2 != type) {
954 printf ("Min clock delay, back-to-back random column addresses "
955 "%d\n", data[15]);
956 }
957
958 puts ("Burst length(s) ");
959 if (data[16] & 0x80) puts (" Page");
960 if (data[16] & 0x08) puts (" 8");
961 if (data[16] & 0x04) puts (" 4");
962 if (data[16] & 0x02) puts (" 2");
963 if (data[16] & 0x01) puts (" 1");
964 putc ('\n');
965 printf ("Number of banks %d\n", data[17]);
966
967 switch (type) {
968 case DDR2:
969 puts ("CAS latency(s) ");
970 decode_bits (data[18], decode_CAS_DDR2, 0);
971 putc ('\n');
972 break;
973 default:
974 puts ("CAS latency(s) ");
975 decode_bits (data[18], decode_CAS_default, 0);
976 putc ('\n');
977 break;
978 }
979
980 if (DDR2 != type) {
981 puts ("CS latency(s) ");
982 decode_bits (data[19], decode_CS_WE_default, 0);
983 putc ('\n');
984 }
985
986 if (DDR2 != type) {
987 puts ("WE latency(s) ");
988 decode_bits (data[20], decode_CS_WE_default, 0);
989 putc ('\n');
990 }
991
992 switch (type) {
993 case DDR2:
994 puts ("Module attributes:\n");
995 if (data[21] & 0x80)
996 puts (" TBD (bit 7)\n");
997 if (data[21] & 0x40)
998 puts (" Analysis probe installed\n");
999 if (data[21] & 0x20)
1000 puts (" TBD (bit 5)\n");
1001 if (data[21] & 0x10)
1002 puts (" FET switch external enable\n");
1003 printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
1004 if (data[20] & 0x11) {
1005 printf (" %d active registers on DIMM\n",
1006 (data[21] & 0x03) + 1);
1007 }
1008 break;
1009 default:
1010 puts ("Module attributes:\n");
1011 if (!data[21])
1012 puts (" (none)\n");
1013 else
1014 decode_bits (data[21], decode_byte21_default, 0);
1015 break;
1016 }
1017
1018 switch (type) {
1019 case DDR2:
1020 decode_bits (data[22], decode_byte22_DDR2, 0);
1021 break;
1022 default:
1023 puts ("Device attributes:\n");
1024 if (data[22] & 0x80) puts (" TBD (bit 7)\n");
1025 if (data[22] & 0x40) puts (" TBD (bit 6)\n");
1026 if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
1027 else puts (" Upper Vcc tolerance 10%\n");
1028 if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
1029 else puts (" Lower Vcc tolerance 10%\n");
1030 if (data[22] & 0x08) puts (" Supports write1/read burst\n");
1031 if (data[22] & 0x04) puts (" Supports precharge all\n");
1032 if (data[22] & 0x02) puts (" Supports auto precharge\n");
1033 if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
1034 break;
1035 }
1036
1037 switch (type) {
1038 case DDR2:
1039 printf ("SDRAM cycle time (2nd highest CAS latency) ");
1040 print_ddr2_tcyc (data[23]);
1041 break;
1042 default:
1043 printf ("SDRAM cycle time (2nd highest CAS latency) %d."
1044 "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
1045 break;
1046 }
1047
1048 switch (type) {
1049 case DDR2:
1050 printf ("SDRAM access from clock (2nd highest CAS latency) 0."
1051 "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1052 break;
1053 default:
1054 printf ("SDRAM access from clock (2nd highest CAS latency) %d."
1055 "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1056 break;
1057 }
1058
1059 switch (type) {
1060 case DDR2:
1061 printf ("SDRAM cycle time (3rd highest CAS latency) ");
1062 print_ddr2_tcyc (data[25]);
1063 break;
1064 default:
1065 printf ("SDRAM cycle time (3rd highest CAS latency) %d."
1066 "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
1067 break;
1068 }
1069
1070 switch (type) {
1071 case DDR2:
1072 printf ("SDRAM access from clock (3rd highest CAS latency) 0."
1073 "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1074 break;
1075 default:
1076 printf ("SDRAM access from clock (3rd highest CAS latency) %d."
1077 "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1078 break;
1079 }
1080
1081 switch (type) {
1082 case DDR2:
1083 printf ("Minimum row precharge %d.%02d ns\n",
1084 (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
1085 break;
1086 default:
1087 printf ("Minimum row precharge %d ns\n", data[27]);
1088 break;
1089 }
1090
1091 switch (type) {
1092 case DDR2:
1093 printf ("Row active to row active min %d.%02d ns\n",
1094 (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
1095 break;
1096 default:
1097 printf ("Row active to row active min %d ns\n", data[28]);
1098 break;
1099 }
1100
1101 switch (type) {
1102 case DDR2:
1103 printf ("RAS to CAS delay min %d.%02d ns\n",
1104 (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
1105 break;
1106 default:
1107 printf ("RAS to CAS delay min %d ns\n", data[29]);
1108 break;
1109 }
1110
1111 printf ("Minimum RAS pulse width %d ns\n", data[30]);
1112
1113 switch (type) {
1114 case DDR2:
1115 puts ("Density of each row ");
1116 decode_bits (data[31], decode_row_density_DDR2, 1);
1117 putc ('\n');
1118 break;
1119 default:
1120 puts ("Density of each row ");
1121 decode_bits (data[31], decode_row_density_default, 1);
1122 putc ('\n');
1123 break;
1124 }
1125
1126 switch (type) {
1127 case DDR2:
1128 puts ("Command and Address setup ");
1129 if (data[32] >= 0xA0) {
1130 printf ("1.%d%d ns\n",
1131 ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
1132 } else {
1133 printf ("0.%d%d ns\n",
1134 ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
1135 }
1136 break;
1137 default:
1138 printf ("Command and Address setup %c%d.%d ns\n",
1139 (data[32] & 0x80) ? '-' : '+',
1140 (data[32] >> 4) & 0x07, data[32] & 0x0F);
1141 break;
1142 }
1143
1144 switch (type) {
1145 case DDR2:
1146 puts ("Command and Address hold ");
1147 if (data[33] >= 0xA0) {
1148 printf ("1.%d%d ns\n",
1149 ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
1150 } else {
1151 printf ("0.%d%d ns\n",
1152 ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
1153 }
1154 break;
1155 default:
1156 printf ("Command and Address hold %c%d.%d ns\n",
1157 (data[33] & 0x80) ? '-' : '+',
1158 (data[33] >> 4) & 0x07, data[33] & 0x0F);
1159 break;
1160 }
1161
1162 switch (type) {
1163 case DDR2:
1164 printf ("Data signal input setup 0.%d%d ns\n",
1165 (data[34] >> 4) & 0x0F, data[34] & 0x0F);
1166 break;
1167 default:
1168 printf ("Data signal input setup %c%d.%d ns\n",
1169 (data[34] & 0x80) ? '-' : '+',
1170 (data[34] >> 4) & 0x07, data[34] & 0x0F);
1171 break;
1172 }
1173
1174 switch (type) {
1175 case DDR2:
1176 printf ("Data signal input hold 0.%d%d ns\n",
1177 (data[35] >> 4) & 0x0F, data[35] & 0x0F);
1178 break;
1179 default:
1180 printf ("Data signal input hold %c%d.%d ns\n",
1181 (data[35] & 0x80) ? '-' : '+',
1182 (data[35] >> 4) & 0x07, data[35] & 0x0F);
1183 break;
1184 }
1185
1186 puts ("Manufacturer's JEDEC ID ");
1187 for (j = 64; j <= 71; j++)
1188 printf ("%02X ", data[j]);
1189 putc ('\n');
1190 printf ("Manufacturing Location %02X\n", data[72]);
1191 puts ("Manufacturer's Part Number ");
1192 for (j = 73; j <= 90; j++)
1193 printf ("%02X ", data[j]);
1194 putc ('\n');
1195 printf ("Revision Code %02X %02X\n", data[91], data[92]);
1196 printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
1197 puts ("Assembly Serial Number ");
1198 for (j = 95; j <= 98; j++)
1199 printf ("%02X ", data[j]);
1200 putc ('\n');
1201
1202 if (DDR2 != type) {
1203 printf ("Speed rating PC%d\n",
1204 data[126] == 0x66 ? 66 : data[126]);
1205 }
1206 return 0;
1207 }
1208 #endif
1209
1210 #if defined(CONFIG_I2C_MUX)
1211 static int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1212 {
1213 int ret=0;
1214
1215 if (argc == 1) {
1216 /* show all busses */
1217 I2C_MUX *mux;
1218 I2C_MUX_DEVICE *device = i2c_mux_devices;
1219
1220 printf ("Busses reached over muxes:\n");
1221 while (device != NULL) {
1222 printf ("Bus ID: %x\n", device->busid);
1223 printf (" reached over Mux(es):\n");
1224 mux = device->mux;
1225 while (mux != NULL) {
1226 printf (" %s@%x ch: %x\n", mux->name, mux->chip, mux->channel);
1227 mux = mux->next;
1228 }
1229 device = device->next;
1230 }
1231 } else {
1232 I2C_MUX_DEVICE *dev;
1233
1234 dev = i2c_mux_ident_muxstring ((uchar *)argv[1]);
1235 ret = 0;
1236 }
1237 return ret;
1238 }
1239 #endif /* CONFIG_I2C_MUX */
1240
1241 #if defined(CONFIG_I2C_MULTI_BUS)
1242 static int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1243 {
1244 int bus_idx, ret=0;
1245
1246 if (argc == 1)
1247 /* querying current setting */
1248 printf("Current bus is %d\n", i2c_get_bus_num());
1249 else {
1250 bus_idx = simple_strtoul(argv[1], NULL, 10);
1251 printf("Setting bus to %d\n", bus_idx);
1252 ret = i2c_set_bus_num(bus_idx);
1253 if (ret)
1254 printf("Failure changing bus number (%d)\n", ret);
1255 }
1256 return ret;
1257 }
1258 #endif /* CONFIG_I2C_MULTI_BUS */
1259
1260 static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1261 {
1262 int speed, ret=0;
1263
1264 if (argc == 1)
1265 /* querying current speed */
1266 printf("Current bus speed=%d\n", i2c_get_bus_speed());
1267 else {
1268 speed = simple_strtoul(argv[1], NULL, 10);
1269 printf("Setting bus speed to %d Hz\n", speed);
1270 ret = i2c_set_bus_speed(speed);
1271 if (ret)
1272 printf("Failure changing bus speed (%d)\n", ret);
1273 }
1274 return ret;
1275 }
1276
1277 static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1278 {
1279 return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
1280 }
1281
1282 static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1283 {
1284 return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
1285 }
1286
1287 static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1288 {
1289 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
1290 return 0;
1291 }
1292
1293 static cmd_tbl_t cmd_i2c_sub[] = {
1294 #if defined(CONFIG_I2C_MUX)
1295 U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_add_bus, "", ""),
1296 #endif /* CONFIG_I2C_MUX */
1297 U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
1298 #if defined(CONFIG_I2C_MULTI_BUS)
1299 U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
1300 #endif /* CONFIG_I2C_MULTI_BUS */
1301 U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""),
1302 U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""),
1303 U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""),
1304 U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""),
1305 U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
1306 U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
1307 U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
1308 U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
1309 #if defined(CONFIG_CMD_SDRAM)
1310 U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
1311 #endif
1312 U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
1313 };
1314
1315 static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1316 {
1317 cmd_tbl_t *c;
1318
1319 /* Strip off leading 'i2c' command argument */
1320 argc--;
1321 argv++;
1322
1323 c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));
1324
1325 if (c) {
1326 return c->cmd(cmdtp, flag, argc, argv);
1327 } else {
1328 cmd_usage(cmdtp);
1329 return 1;
1330 }
1331 }
1332
1333 /***************************************************/
1334
1335 U_BOOT_CMD(
1336 i2c, 6, 1, do_i2c,
1337 "I2C sub-system",
1338 #if defined(CONFIG_I2C_MUX)
1339 "bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\ni2c "
1340 #endif /* CONFIG_I2C_MUX */
1341 "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
1342 #if defined(CONFIG_I2C_MULTI_BUS)
1343 "i2c dev [dev] - show or set current I2C bus\n"
1344 #endif /* CONFIG_I2C_MULTI_BUS */
1345 "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
1346 "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
1347 "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
1348 "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
1349 "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
1350 "i2c probe - show devices on the I2C bus\n"
1351 "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n"
1352 "i2c reset - re-init the I2C Controller\n"
1353 #if defined(CONFIG_CMD_SDRAM)
1354 "i2c sdram chip - print SDRAM configuration information\n"
1355 #endif
1356 "i2c speed [speed] - show or set I2C bus speed"
1357 );
1358
1359 #if defined(CONFIG_I2C_MUX)
1360 static int i2c_mux_add_device(I2C_MUX_DEVICE *dev)
1361 {
1362 I2C_MUX_DEVICE *devtmp = i2c_mux_devices;
1363
1364 if (i2c_mux_devices == NULL) {
1365 i2c_mux_devices = dev;
1366 return 0;
1367 }
1368 while (devtmp->next != NULL)
1369 devtmp = devtmp->next;
1370
1371 devtmp->next = dev;
1372 return 0;
1373 }
1374
1375 I2C_MUX_DEVICE *i2c_mux_search_device(int id)
1376 {
1377 I2C_MUX_DEVICE *device = i2c_mux_devices;
1378
1379 while (device != NULL) {
1380 if (device->busid == id)
1381 return device;
1382 device = device->next;
1383 }
1384 return NULL;
1385 }
1386
1387 /* searches in the buf from *pos the next ':'.
1388 * returns:
1389 * 0 if found (with *pos = where)
1390 * < 0 if an error occured
1391 * > 0 if the end of buf is reached
1392 */
1393 static int i2c_mux_search_next (int *pos, uchar *buf, int len)
1394 {
1395 while ((buf[*pos] != ':') && (*pos < len)) {
1396 *pos += 1;
1397 }
1398 if (*pos >= len)
1399 return 1;
1400 if (buf[*pos] != ':')
1401 return -1;
1402 return 0;
1403 }
1404
1405 static int i2c_mux_get_busid (void)
1406 {
1407 int tmp = i2c_mux_busid;
1408
1409 i2c_mux_busid ++;
1410 return tmp;
1411 }
1412
1413 /* Analyses a Muxstring and sends immediately the
1414 Commands to the Muxes. Runs from Flash.
1415 */
1416 int i2c_mux_ident_muxstring_f (uchar *buf)
1417 {
1418 int pos = 0;
1419 int oldpos;
1420 int ret = 0;
1421 int len = strlen((char *)buf);
1422 int chip;
1423 uchar channel;
1424 int was = 0;
1425
1426 while (ret == 0) {
1427 oldpos = pos;
1428 /* search name */
1429 ret = i2c_mux_search_next(&pos, buf, len);
1430 if (ret != 0)
1431 printf ("ERROR\n");
1432 /* search address */
1433 pos ++;
1434 oldpos = pos;
1435 ret = i2c_mux_search_next(&pos, buf, len);
1436 if (ret != 0)
1437 printf ("ERROR\n");
1438 buf[pos] = 0;
1439 chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1440 buf[pos] = ':';
1441 /* search channel */
1442 pos ++;
1443 oldpos = pos;
1444 ret = i2c_mux_search_next(&pos, buf, len);
1445 if (ret < 0)
1446 printf ("ERROR\n");
1447 was = 0;
1448 if (buf[pos] != 0) {
1449 buf[pos] = 0;
1450 was = 1;
1451 }
1452 channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1453 if (was)
1454 buf[pos] = ':';
1455 if (i2c_write(chip, 0, 0, &channel, 1) != 0) {
1456 printf ("Error setting Mux: chip:%x channel: \
1457 %x\n", chip, channel);
1458 return -1;
1459 }
1460 pos ++;
1461 oldpos = pos;
1462
1463 }
1464
1465 return 0;
1466 }
1467
1468 /* Analyses a Muxstring and if this String is correct
1469 * adds a new I2C Bus.
1470 */
1471 I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf)
1472 {
1473 I2C_MUX_DEVICE *device;
1474 I2C_MUX *mux;
1475 int pos = 0;
1476 int oldpos;
1477 int ret = 0;
1478 int len = strlen((char *)buf);
1479 int was = 0;
1480
1481 device = (I2C_MUX_DEVICE *)malloc (sizeof(I2C_MUX_DEVICE));
1482 device->mux = NULL;
1483 device->busid = i2c_mux_get_busid ();
1484 device->next = NULL;
1485 while (ret == 0) {
1486 mux = (I2C_MUX *)malloc (sizeof(I2C_MUX));
1487 mux->next = NULL;
1488 /* search name of mux */
1489 oldpos = pos;
1490 ret = i2c_mux_search_next(&pos, buf, len);
1491 if (ret != 0)
1492 printf ("%s no name.\n", __FUNCTION__);
1493 mux->name = (char *)malloc (pos - oldpos + 1);
1494 memcpy (mux->name, &buf[oldpos], pos - oldpos);
1495 mux->name[pos - oldpos] = 0;
1496 /* search address */
1497 pos ++;
1498 oldpos = pos;
1499 ret = i2c_mux_search_next(&pos, buf, len);
1500 if (ret != 0)
1501 printf ("%s no mux address.\n", __FUNCTION__);
1502 buf[pos] = 0;
1503 mux->chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1504 buf[pos] = ':';
1505 /* search channel */
1506 pos ++;
1507 oldpos = pos;
1508 ret = i2c_mux_search_next(&pos, buf, len);
1509 if (ret < 0)
1510 printf ("%s no mux channel.\n", __FUNCTION__);
1511 was = 0;
1512 if (buf[pos] != 0) {
1513 buf[pos] = 0;
1514 was = 1;
1515 }
1516 mux->channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1517 if (was)
1518 buf[pos] = ':';
1519 if (device->mux == NULL)
1520 device->mux = mux;
1521 else {
1522 I2C_MUX *muxtmp = device->mux;
1523 while (muxtmp->next != NULL) {
1524 muxtmp = muxtmp->next;
1525 }
1526 muxtmp->next = mux;
1527 }
1528 pos ++;
1529 oldpos = pos;
1530 }
1531 if (ret > 0) {
1532 /* Add Device */
1533 i2c_mux_add_device (device);
1534 return device;
1535 }
1536
1537 return NULL;
1538 }
1539
1540 int i2x_mux_select_mux(int bus)
1541 {
1542 I2C_MUX_DEVICE *dev;
1543 I2C_MUX *mux;
1544
1545 if ((gd->flags & GD_FLG_RELOC) != GD_FLG_RELOC) {
1546 /* select Default Mux Bus */
1547 #if defined(CONFIG_SYS_I2C_IVM_BUS)
1548 i2c_mux_ident_muxstring_f ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
1549 #else
1550 {
1551 unsigned char *buf;
1552 buf = (unsigned char *) getenv("EEprom_ivm");
1553 if (buf != NULL)
1554 i2c_mux_ident_muxstring_f (buf);
1555 }
1556 #endif
1557 return 0;
1558 }
1559 dev = i2c_mux_search_device(bus);
1560 if (dev == NULL)
1561 return -1;
1562
1563 mux = dev->mux;
1564 while (mux != NULL) {
1565 if (i2c_write(mux->chip, 0, 0, &mux->channel, 1) != 0) {
1566 printf ("Error setting Mux: chip:%x channel: \
1567 %x\n", mux->chip, mux->channel);
1568 return -1;
1569 }
1570 mux = mux->next;
1571 }
1572 return 0;
1573 }
1574 #endif /* CONFIG_I2C_MUX */