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i2c: Remove deprecated individual i2c commands
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1 /*
2 * (C) Copyright 2001
3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 * I2C Functions similar to the standard memory functions.
26 *
27 * There are several parameters in many of the commands that bear further
28 * explanations:
29 *
30 * Two of the commands (imm and imw) take a byte/word/long modifier
31 * (e.g. imm.w specifies the word-length modifier). This was done to
32 * allow manipulating word-length registers. It was not done on any other
33 * commands because it was not deemed useful.
34 *
35 * {i2c_chip} is the I2C chip address (the first byte sent on the bus).
36 * Each I2C chip on the bus has a unique address. On the I2C data bus,
37 * the address is the upper seven bits and the LSB is the "read/write"
38 * bit. Note that the {i2c_chip} address specified on the command
39 * line is not shifted up: e.g. a typical EEPROM memory chip may have
40 * an I2C address of 0x50, but the data put on the bus will be 0xA0
41 * for write and 0xA1 for read. This "non shifted" address notation
42 * matches at least half of the data sheets :-/.
43 *
44 * {addr} is the address (or offset) within the chip. Small memory
45 * chips have 8 bit addresses. Large memory chips have 16 bit
46 * addresses. Other memory chips have 9, 10, or 11 bit addresses.
47 * Many non-memory chips have multiple registers and {addr} is used
48 * as the register index. Some non-memory chips have only one register
49 * and therefore don't need any {addr} parameter.
50 *
51 * The default {addr} parameter is one byte (.1) which works well for
52 * memories and registers with 8 bits of address space.
53 *
54 * You can specify the length of the {addr} field with the optional .0,
55 * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are
56 * manipulating a single register device which doesn't use an address
57 * field, use "0.0" for the address and the ".0" length field will
58 * suppress the address in the I2C data stream. This also works for
59 * successive reads using the I2C auto-incrementing memory pointer.
60 *
61 * If you are manipulating a large memory with 2-byte addresses, use
62 * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal).
63 *
64 * Then there are the unfortunate memory chips that spill the most
65 * significant 1, 2, or 3 bits of address into the chip address byte.
66 * This effectively makes one chip (logically) look like 2, 4, or
67 * 8 chips. This is handled (awkwardly) by #defining
68 * CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
69 * {addr} field (since .1 is the default, it doesn't actually have to
70 * be specified). Examples: given a memory chip at I2C chip address
71 * 0x50, the following would happen...
72 * imd 50 0 10 display 16 bytes starting at 0x000
73 * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
74 * imd 50 100 10 display 16 bytes starting at 0x100
75 * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
76 * imd 50 210 10 display 16 bytes starting at 0x210
77 * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
78 * This is awfully ugly. It would be nice if someone would think up
79 * a better way of handling this.
80 *
81 * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de).
82 */
83
84 #include <common.h>
85 #include <command.h>
86 #include <environment.h>
87 #include <i2c.h>
88 #include <malloc.h>
89 #include <asm/byteorder.h>
90
91 /* Display values from last command.
92 * Memory modify remembered values are different from display memory.
93 */
94 static uchar i2c_dp_last_chip;
95 static uint i2c_dp_last_addr;
96 static uint i2c_dp_last_alen;
97 static uint i2c_dp_last_length = 0x10;
98
99 static uchar i2c_mm_last_chip;
100 static uint i2c_mm_last_addr;
101 static uint i2c_mm_last_alen;
102
103 /* If only one I2C bus is present, the list of devices to ignore when
104 * the probe command is issued is represented by a 1D array of addresses.
105 * When multiple buses are present, the list is an array of bus-address
106 * pairs. The following macros take care of this */
107
108 #if defined(CONFIG_SYS_I2C_NOPROBES)
109 #if defined(CONFIG_I2C_MULTI_BUS)
110 static struct
111 {
112 uchar bus;
113 uchar addr;
114 } i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
115 #define GET_BUS_NUM i2c_get_bus_num()
116 #define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
117 #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
118 #define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
119 #else /* single bus */
120 static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
121 #define GET_BUS_NUM 0
122 #define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
123 #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
124 #define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
125 #endif /* CONFIG_MULTI_BUS */
126
127 #define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0]))
128 #endif
129
130 #if defined(CONFIG_I2C_MUX)
131 static I2C_MUX_DEVICE *i2c_mux_devices = NULL;
132 static int i2c_mux_busid = CONFIG_SYS_MAX_I2C_BUS;
133
134 DECLARE_GLOBAL_DATA_PTR;
135
136 #endif
137
138 static int
139 mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]);
140
141 /* TODO: Implement architecture-specific get/set functions */
142 unsigned int __def_i2c_get_bus_speed(void)
143 {
144 return CONFIG_SYS_I2C_SPEED;
145 }
146 unsigned int i2c_get_bus_speed(void)
147 __attribute__((weak, alias("__def_i2c_get_bus_speed")));
148
149 int __def_i2c_set_bus_speed(unsigned int speed)
150 {
151 if (speed != CONFIG_SYS_I2C_SPEED)
152 return -1;
153
154 return 0;
155 }
156 int i2c_set_bus_speed(unsigned int)
157 __attribute__((weak, alias("__def_i2c_set_bus_speed")));
158
159 /*
160 * Syntax:
161 * imd {i2c_chip} {addr}{.0, .1, .2} {len}
162 */
163 #define DISP_LINE_LEN 16
164
165 int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
166 {
167 u_char chip;
168 uint addr, alen, length;
169 int j, nbytes, linebytes;
170
171 /* We use the last specified parameters, unless new ones are
172 * entered.
173 */
174 chip = i2c_dp_last_chip;
175 addr = i2c_dp_last_addr;
176 alen = i2c_dp_last_alen;
177 length = i2c_dp_last_length;
178
179 if (argc < 3) {
180 cmd_usage(cmdtp);
181 return 1;
182 }
183
184 if ((flag & CMD_FLAG_REPEAT) == 0) {
185 /*
186 * New command specified.
187 */
188 alen = 1;
189
190 /*
191 * I2C chip address
192 */
193 chip = simple_strtoul(argv[1], NULL, 16);
194
195 /*
196 * I2C data address within the chip. This can be 1 or
197 * 2 bytes long. Some day it might be 3 bytes long :-).
198 */
199 addr = simple_strtoul(argv[2], NULL, 16);
200 alen = 1;
201 for (j = 0; j < 8; j++) {
202 if (argv[2][j] == '.') {
203 alen = argv[2][j+1] - '0';
204 if (alen > 4) {
205 cmd_usage(cmdtp);
206 return 1;
207 }
208 break;
209 } else if (argv[2][j] == '\0')
210 break;
211 }
212
213 /*
214 * If another parameter, it is the length to display.
215 * Length is the number of objects, not number of bytes.
216 */
217 if (argc > 3)
218 length = simple_strtoul(argv[3], NULL, 16);
219 }
220
221 /*
222 * Print the lines.
223 *
224 * We buffer all read data, so we can make sure data is read only
225 * once.
226 */
227 nbytes = length;
228 do {
229 unsigned char linebuf[DISP_LINE_LEN];
230 unsigned char *cp;
231
232 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
233
234 if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
235 puts ("Error reading the chip.\n");
236 else {
237 printf("%04x:", addr);
238 cp = linebuf;
239 for (j=0; j<linebytes; j++) {
240 printf(" %02x", *cp++);
241 addr++;
242 }
243 puts (" ");
244 cp = linebuf;
245 for (j=0; j<linebytes; j++) {
246 if ((*cp < 0x20) || (*cp > 0x7e))
247 puts (".");
248 else
249 printf("%c", *cp);
250 cp++;
251 }
252 putc ('\n');
253 }
254 nbytes -= linebytes;
255 } while (nbytes > 0);
256
257 i2c_dp_last_chip = chip;
258 i2c_dp_last_addr = addr;
259 i2c_dp_last_alen = alen;
260 i2c_dp_last_length = length;
261
262 return 0;
263 }
264
265 int do_i2c_mm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
266 {
267 return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
268 }
269
270 int do_i2c_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
271 {
272 return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
273 }
274
275 /* Write (fill) memory
276 *
277 * Syntax:
278 * imw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
279 */
280 int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
281 {
282 uchar chip;
283 ulong addr;
284 uint alen;
285 uchar byte;
286 int count;
287 int j;
288
289 if ((argc < 4) || (argc > 5)) {
290 cmd_usage(cmdtp);
291 return 1;
292 }
293
294 /*
295 * Chip is always specified.
296 */
297 chip = simple_strtoul(argv[1], NULL, 16);
298
299 /*
300 * Address is always specified.
301 */
302 addr = simple_strtoul(argv[2], NULL, 16);
303 alen = 1;
304 for (j = 0; j < 8; j++) {
305 if (argv[2][j] == '.') {
306 alen = argv[2][j+1] - '0';
307 if (alen > 4) {
308 cmd_usage(cmdtp);
309 return 1;
310 }
311 break;
312 } else if (argv[2][j] == '\0')
313 break;
314 }
315
316 /*
317 * Value to write is always specified.
318 */
319 byte = simple_strtoul(argv[3], NULL, 16);
320
321 /*
322 * Optional count
323 */
324 if (argc == 5)
325 count = simple_strtoul(argv[4], NULL, 16);
326 else
327 count = 1;
328
329 while (count-- > 0) {
330 if (i2c_write(chip, addr++, alen, &byte, 1) != 0)
331 puts ("Error writing the chip.\n");
332 /*
333 * Wait for the write to complete. The write can take
334 * up to 10mSec (we allow a little more time).
335 *
336 * On some chips, while the write is in progress, the
337 * chip doesn't respond. This apparently isn't a
338 * universal feature so we don't take advantage of it.
339 */
340 /*
341 * No write delay with FRAM devices.
342 */
343 #if !defined(CONFIG_SYS_I2C_FRAM)
344 udelay(11000);
345 #endif
346
347 #if 0
348 for (timeout = 0; timeout < 10; timeout++) {
349 udelay(2000);
350 if (i2c_probe(chip) == 0)
351 break;
352 }
353 #endif
354 }
355
356 return (0);
357 }
358
359 /* Calculate a CRC on memory
360 *
361 * Syntax:
362 * icrc32 {i2c_chip} {addr}{.0, .1, .2} {count}
363 */
364 int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
365 {
366 uchar chip;
367 ulong addr;
368 uint alen;
369 int count;
370 uchar byte;
371 ulong crc;
372 ulong err;
373 int j;
374
375 if (argc < 4) {
376 cmd_usage(cmdtp);
377 return 1;
378 }
379
380 /*
381 * Chip is always specified.
382 */
383 chip = simple_strtoul(argv[1], NULL, 16);
384
385 /*
386 * Address is always specified.
387 */
388 addr = simple_strtoul(argv[2], NULL, 16);
389 alen = 1;
390 for (j = 0; j < 8; j++) {
391 if (argv[2][j] == '.') {
392 alen = argv[2][j+1] - '0';
393 if (alen > 4) {
394 cmd_usage(cmdtp);
395 return 1;
396 }
397 break;
398 } else if (argv[2][j] == '\0')
399 break;
400 }
401
402 /*
403 * Count is always specified
404 */
405 count = simple_strtoul(argv[3], NULL, 16);
406
407 printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
408 /*
409 * CRC a byte at a time. This is going to be slooow, but hey, the
410 * memories are small and slow too so hopefully nobody notices.
411 */
412 crc = 0;
413 err = 0;
414 while (count-- > 0) {
415 if (i2c_read(chip, addr, alen, &byte, 1) != 0)
416 err++;
417 crc = crc32 (crc, &byte, 1);
418 addr++;
419 }
420 if (err > 0)
421 puts ("Error reading the chip,\n");
422 else
423 printf ("%08lx\n", crc);
424
425 return 0;
426 }
427
428 /* Modify memory.
429 *
430 * Syntax:
431 * imm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
432 * inm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
433 */
434
435 static int
436 mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
437 {
438 uchar chip;
439 ulong addr;
440 uint alen;
441 ulong data;
442 int size = 1;
443 int nbytes;
444 int j;
445 extern char console_buffer[];
446
447 if (argc != 3) {
448 cmd_usage(cmdtp);
449 return 1;
450 }
451
452 #ifdef CONFIG_BOOT_RETRY_TIME
453 reset_cmd_timeout(); /* got a good command to get here */
454 #endif
455 /*
456 * We use the last specified parameters, unless new ones are
457 * entered.
458 */
459 chip = i2c_mm_last_chip;
460 addr = i2c_mm_last_addr;
461 alen = i2c_mm_last_alen;
462
463 if ((flag & CMD_FLAG_REPEAT) == 0) {
464 /*
465 * New command specified. Check for a size specification.
466 * Defaults to byte if no or incorrect specification.
467 */
468 size = cmd_get_data_size(argv[0], 1);
469
470 /*
471 * Chip is always specified.
472 */
473 chip = simple_strtoul(argv[1], NULL, 16);
474
475 /*
476 * Address is always specified.
477 */
478 addr = simple_strtoul(argv[2], NULL, 16);
479 alen = 1;
480 for (j = 0; j < 8; j++) {
481 if (argv[2][j] == '.') {
482 alen = argv[2][j+1] - '0';
483 if (alen > 4) {
484 cmd_usage(cmdtp);
485 return 1;
486 }
487 break;
488 } else if (argv[2][j] == '\0')
489 break;
490 }
491 }
492
493 /*
494 * Print the address, followed by value. Then accept input for
495 * the next value. A non-converted value exits.
496 */
497 do {
498 printf("%08lx:", addr);
499 if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0)
500 puts ("\nError reading the chip,\n");
501 else {
502 data = cpu_to_be32(data);
503 if (size == 1)
504 printf(" %02lx", (data >> 24) & 0x000000FF);
505 else if (size == 2)
506 printf(" %04lx", (data >> 16) & 0x0000FFFF);
507 else
508 printf(" %08lx", data);
509 }
510
511 nbytes = readline (" ? ");
512 if (nbytes == 0) {
513 /*
514 * <CR> pressed as only input, don't modify current
515 * location and move to next.
516 */
517 if (incrflag)
518 addr += size;
519 nbytes = size;
520 #ifdef CONFIG_BOOT_RETRY_TIME
521 reset_cmd_timeout(); /* good enough to not time out */
522 #endif
523 }
524 #ifdef CONFIG_BOOT_RETRY_TIME
525 else if (nbytes == -2)
526 break; /* timed out, exit the command */
527 #endif
528 else {
529 char *endp;
530
531 data = simple_strtoul(console_buffer, &endp, 16);
532 if (size == 1)
533 data = data << 24;
534 else if (size == 2)
535 data = data << 16;
536 data = be32_to_cpu(data);
537 nbytes = endp - console_buffer;
538 if (nbytes) {
539 #ifdef CONFIG_BOOT_RETRY_TIME
540 /*
541 * good enough to not time out
542 */
543 reset_cmd_timeout();
544 #endif
545 if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
546 puts ("Error writing the chip.\n");
547 #ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
548 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
549 #endif
550 if (incrflag)
551 addr += size;
552 }
553 }
554 } while (nbytes);
555
556 i2c_mm_last_chip = chip;
557 i2c_mm_last_addr = addr;
558 i2c_mm_last_alen = alen;
559
560 return 0;
561 }
562
563 /*
564 * Syntax:
565 * iprobe {addr}{.0, .1, .2}
566 */
567 int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
568 {
569 int j;
570 #if defined(CONFIG_SYS_I2C_NOPROBES)
571 int k, skip;
572 uchar bus = GET_BUS_NUM;
573 #endif /* NOPROBES */
574
575 puts ("Valid chip addresses:");
576 for (j = 0; j < 128; j++) {
577 #if defined(CONFIG_SYS_I2C_NOPROBES)
578 skip = 0;
579 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
580 if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
581 skip = 1;
582 break;
583 }
584 }
585 if (skip)
586 continue;
587 #endif
588 if (i2c_probe(j) == 0)
589 printf(" %02X", j);
590 }
591 putc ('\n');
592
593 #if defined(CONFIG_SYS_I2C_NOPROBES)
594 puts ("Excluded chip addresses:");
595 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
596 if (COMPARE_BUS(bus,k))
597 printf(" %02X", NO_PROBE_ADDR(k));
598 }
599 putc ('\n');
600 #endif
601
602 return 0;
603 }
604
605 /*
606 * Syntax:
607 * iloop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
608 * {length} - Number of bytes to read
609 * {delay} - A DECIMAL number and defaults to 1000 uSec
610 */
611 int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
612 {
613 u_char chip;
614 ulong alen;
615 uint addr;
616 uint length;
617 u_char bytes[16];
618 int delay;
619 int j;
620
621 if (argc < 3) {
622 cmd_usage(cmdtp);
623 return 1;
624 }
625
626 /*
627 * Chip is always specified.
628 */
629 chip = simple_strtoul(argv[1], NULL, 16);
630
631 /*
632 * Address is always specified.
633 */
634 addr = simple_strtoul(argv[2], NULL, 16);
635 alen = 1;
636 for (j = 0; j < 8; j++) {
637 if (argv[2][j] == '.') {
638 alen = argv[2][j+1] - '0';
639 if (alen > 4) {
640 cmd_usage(cmdtp);
641 return 1;
642 }
643 break;
644 } else if (argv[2][j] == '\0')
645 break;
646 }
647
648 /*
649 * Length is the number of objects, not number of bytes.
650 */
651 length = 1;
652 length = simple_strtoul(argv[3], NULL, 16);
653 if (length > sizeof(bytes))
654 length = sizeof(bytes);
655
656 /*
657 * The delay time (uSec) is optional.
658 */
659 delay = 1000;
660 if (argc > 3)
661 delay = simple_strtoul(argv[4], NULL, 10);
662 /*
663 * Run the loop...
664 */
665 while (1) {
666 if (i2c_read(chip, addr, alen, bytes, length) != 0)
667 puts ("Error reading the chip.\n");
668 udelay(delay);
669 }
670
671 /* NOTREACHED */
672 return 0;
673 }
674
675 /*
676 * The SDRAM command is separately configured because many
677 * (most?) embedded boards don't use SDRAM DIMMs.
678 */
679 #if defined(CONFIG_CMD_SDRAM)
680 static void print_ddr2_tcyc (u_char const b)
681 {
682 printf ("%d.", (b >> 4) & 0x0F);
683 switch (b & 0x0F) {
684 case 0x0:
685 case 0x1:
686 case 0x2:
687 case 0x3:
688 case 0x4:
689 case 0x5:
690 case 0x6:
691 case 0x7:
692 case 0x8:
693 case 0x9:
694 printf ("%d ns\n", b & 0x0F);
695 break;
696 case 0xA:
697 puts ("25 ns\n");
698 break;
699 case 0xB:
700 puts ("33 ns\n");
701 break;
702 case 0xC:
703 puts ("66 ns\n");
704 break;
705 case 0xD:
706 puts ("75 ns\n");
707 break;
708 default:
709 puts ("?? ns\n");
710 break;
711 }
712 }
713
714 static void decode_bits (u_char const b, char const *str[], int const do_once)
715 {
716 u_char mask;
717
718 for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
719 if (b & mask) {
720 puts (*str);
721 if (do_once)
722 return;
723 }
724 }
725 }
726
727 /*
728 * Syntax:
729 * sdram {i2c_chip}
730 */
731 int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
732 {
733 enum { unknown, EDO, SDRAM, DDR2 } type;
734
735 u_char chip;
736 u_char data[128];
737 u_char cksum;
738 int j;
739
740 static const char *decode_CAS_DDR2[] = {
741 " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
742 };
743
744 static const char *decode_CAS_default[] = {
745 " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
746 };
747
748 static const char *decode_CS_WE_default[] = {
749 " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
750 };
751
752 static const char *decode_byte21_default[] = {
753 " TBD (bit 7)\n",
754 " Redundant row address\n",
755 " Differential clock input\n",
756 " Registerd DQMB inputs\n",
757 " Buffered DQMB inputs\n",
758 " On-card PLL\n",
759 " Registered address/control lines\n",
760 " Buffered address/control lines\n"
761 };
762
763 static const char *decode_byte22_DDR2[] = {
764 " TBD (bit 7)\n",
765 " TBD (bit 6)\n",
766 " TBD (bit 5)\n",
767 " TBD (bit 4)\n",
768 " TBD (bit 3)\n",
769 " Supports partial array self refresh\n",
770 " Supports 50 ohm ODT\n",
771 " Supports weak driver\n"
772 };
773
774 static const char *decode_row_density_DDR2[] = {
775 "512 MiB", "256 MiB", "128 MiB", "16 GiB",
776 "8 GiB", "4 GiB", "2 GiB", "1 GiB"
777 };
778
779 static const char *decode_row_density_default[] = {
780 "512 MiB", "256 MiB", "128 MiB", "64 MiB",
781 "32 MiB", "16 MiB", "8 MiB", "4 MiB"
782 };
783
784 if (argc < 2) {
785 cmd_usage(cmdtp);
786 return 1;
787 }
788 /*
789 * Chip is always specified.
790 */
791 chip = simple_strtoul (argv[1], NULL, 16);
792
793 if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
794 puts ("No SDRAM Serial Presence Detect found.\n");
795 return 1;
796 }
797
798 cksum = 0;
799 for (j = 0; j < 63; j++) {
800 cksum += data[j];
801 }
802 if (cksum != data[63]) {
803 printf ("WARNING: Configuration data checksum failure:\n"
804 " is 0x%02x, calculated 0x%02x\n", data[63], cksum);
805 }
806 printf ("SPD data revision %d.%d\n",
807 (data[62] >> 4) & 0x0F, data[62] & 0x0F);
808 printf ("Bytes used 0x%02X\n", data[0]);
809 printf ("Serial memory size 0x%02X\n", 1 << data[1]);
810
811 puts ("Memory type ");
812 switch (data[2]) {
813 case 2:
814 type = EDO;
815 puts ("EDO\n");
816 break;
817 case 4:
818 type = SDRAM;
819 puts ("SDRAM\n");
820 break;
821 case 8:
822 type = DDR2;
823 puts ("DDR2\n");
824 break;
825 default:
826 type = unknown;
827 puts ("unknown\n");
828 break;
829 }
830
831 puts ("Row address bits ");
832 if ((data[3] & 0x00F0) == 0)
833 printf ("%d\n", data[3] & 0x0F);
834 else
835 printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
836
837 puts ("Column address bits ");
838 if ((data[4] & 0x00F0) == 0)
839 printf ("%d\n", data[4] & 0x0F);
840 else
841 printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
842
843 switch (type) {
844 case DDR2:
845 printf ("Number of ranks %d\n",
846 (data[5] & 0x07) + 1);
847 break;
848 default:
849 printf ("Module rows %d\n", data[5]);
850 break;
851 }
852
853 switch (type) {
854 case DDR2:
855 printf ("Module data width %d bits\n", data[6]);
856 break;
857 default:
858 printf ("Module data width %d bits\n",
859 (data[7] << 8) | data[6]);
860 break;
861 }
862
863 puts ("Interface signal levels ");
864 switch(data[8]) {
865 case 0: puts ("TTL 5.0 V\n"); break;
866 case 1: puts ("LVTTL\n"); break;
867 case 2: puts ("HSTL 1.5 V\n"); break;
868 case 3: puts ("SSTL 3.3 V\n"); break;
869 case 4: puts ("SSTL 2.5 V\n"); break;
870 case 5: puts ("SSTL 1.8 V\n"); break;
871 default: puts ("unknown\n"); break;
872 }
873
874 switch (type) {
875 case DDR2:
876 printf ("SDRAM cycle time ");
877 print_ddr2_tcyc (data[9]);
878 break;
879 default:
880 printf ("SDRAM cycle time %d.%d ns\n",
881 (data[9] >> 4) & 0x0F, data[9] & 0x0F);
882 break;
883 }
884
885 switch (type) {
886 case DDR2:
887 printf ("SDRAM access time 0.%d%d ns\n",
888 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
889 break;
890 default:
891 printf ("SDRAM access time %d.%d ns\n",
892 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
893 break;
894 }
895
896 puts ("EDC configuration ");
897 switch (data[11]) {
898 case 0: puts ("None\n"); break;
899 case 1: puts ("Parity\n"); break;
900 case 2: puts ("ECC\n"); break;
901 default: puts ("unknown\n"); break;
902 }
903
904 if ((data[12] & 0x80) == 0)
905 puts ("No self refresh, rate ");
906 else
907 puts ("Self refresh, rate ");
908
909 switch(data[12] & 0x7F) {
910 case 0: puts ("15.625 us\n"); break;
911 case 1: puts ("3.9 us\n"); break;
912 case 2: puts ("7.8 us\n"); break;
913 case 3: puts ("31.3 us\n"); break;
914 case 4: puts ("62.5 us\n"); break;
915 case 5: puts ("125 us\n"); break;
916 default: puts ("unknown\n"); break;
917 }
918
919 switch (type) {
920 case DDR2:
921 printf ("SDRAM width (primary) %d\n", data[13]);
922 break;
923 default:
924 printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
925 if ((data[13] & 0x80) != 0) {
926 printf (" (second bank) %d\n",
927 2 * (data[13] & 0x7F));
928 }
929 break;
930 }
931
932 switch (type) {
933 case DDR2:
934 if (data[14] != 0)
935 printf ("EDC width %d\n", data[14]);
936 break;
937 default:
938 if (data[14] != 0) {
939 printf ("EDC width %d\n",
940 data[14] & 0x7F);
941
942 if ((data[14] & 0x80) != 0) {
943 printf (" (second bank) %d\n",
944 2 * (data[14] & 0x7F));
945 }
946 }
947 break;
948 }
949
950 if (DDR2 != type) {
951 printf ("Min clock delay, back-to-back random column addresses "
952 "%d\n", data[15]);
953 }
954
955 puts ("Burst length(s) ");
956 if (data[16] & 0x80) puts (" Page");
957 if (data[16] & 0x08) puts (" 8");
958 if (data[16] & 0x04) puts (" 4");
959 if (data[16] & 0x02) puts (" 2");
960 if (data[16] & 0x01) puts (" 1");
961 putc ('\n');
962 printf ("Number of banks %d\n", data[17]);
963
964 switch (type) {
965 case DDR2:
966 puts ("CAS latency(s) ");
967 decode_bits (data[18], decode_CAS_DDR2, 0);
968 putc ('\n');
969 break;
970 default:
971 puts ("CAS latency(s) ");
972 decode_bits (data[18], decode_CAS_default, 0);
973 putc ('\n');
974 break;
975 }
976
977 if (DDR2 != type) {
978 puts ("CS latency(s) ");
979 decode_bits (data[19], decode_CS_WE_default, 0);
980 putc ('\n');
981 }
982
983 if (DDR2 != type) {
984 puts ("WE latency(s) ");
985 decode_bits (data[20], decode_CS_WE_default, 0);
986 putc ('\n');
987 }
988
989 switch (type) {
990 case DDR2:
991 puts ("Module attributes:\n");
992 if (data[21] & 0x80)
993 puts (" TBD (bit 7)\n");
994 if (data[21] & 0x40)
995 puts (" Analysis probe installed\n");
996 if (data[21] & 0x20)
997 puts (" TBD (bit 5)\n");
998 if (data[21] & 0x10)
999 puts (" FET switch external enable\n");
1000 printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
1001 if (data[20] & 0x11) {
1002 printf (" %d active registers on DIMM\n",
1003 (data[21] & 0x03) + 1);
1004 }
1005 break;
1006 default:
1007 puts ("Module attributes:\n");
1008 if (!data[21])
1009 puts (" (none)\n");
1010 else
1011 decode_bits (data[21], decode_byte21_default, 0);
1012 break;
1013 }
1014
1015 switch (type) {
1016 case DDR2:
1017 decode_bits (data[22], decode_byte22_DDR2, 0);
1018 break;
1019 default:
1020 puts ("Device attributes:\n");
1021 if (data[22] & 0x80) puts (" TBD (bit 7)\n");
1022 if (data[22] & 0x40) puts (" TBD (bit 6)\n");
1023 if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
1024 else puts (" Upper Vcc tolerance 10%\n");
1025 if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
1026 else puts (" Lower Vcc tolerance 10%\n");
1027 if (data[22] & 0x08) puts (" Supports write1/read burst\n");
1028 if (data[22] & 0x04) puts (" Supports precharge all\n");
1029 if (data[22] & 0x02) puts (" Supports auto precharge\n");
1030 if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
1031 break;
1032 }
1033
1034 switch (type) {
1035 case DDR2:
1036 printf ("SDRAM cycle time (2nd highest CAS latency) ");
1037 print_ddr2_tcyc (data[23]);
1038 break;
1039 default:
1040 printf ("SDRAM cycle time (2nd highest CAS latency) %d."
1041 "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
1042 break;
1043 }
1044
1045 switch (type) {
1046 case DDR2:
1047 printf ("SDRAM access from clock (2nd highest CAS latency) 0."
1048 "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1049 break;
1050 default:
1051 printf ("SDRAM access from clock (2nd highest CAS latency) %d."
1052 "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1053 break;
1054 }
1055
1056 switch (type) {
1057 case DDR2:
1058 printf ("SDRAM cycle time (3rd highest CAS latency) ");
1059 print_ddr2_tcyc (data[25]);
1060 break;
1061 default:
1062 printf ("SDRAM cycle time (3rd highest CAS latency) %d."
1063 "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
1064 break;
1065 }
1066
1067 switch (type) {
1068 case DDR2:
1069 printf ("SDRAM access from clock (3rd highest CAS latency) 0."
1070 "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1071 break;
1072 default:
1073 printf ("SDRAM access from clock (3rd highest CAS latency) %d."
1074 "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1075 break;
1076 }
1077
1078 switch (type) {
1079 case DDR2:
1080 printf ("Minimum row precharge %d.%02d ns\n",
1081 (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
1082 break;
1083 default:
1084 printf ("Minimum row precharge %d ns\n", data[27]);
1085 break;
1086 }
1087
1088 switch (type) {
1089 case DDR2:
1090 printf ("Row active to row active min %d.%02d ns\n",
1091 (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
1092 break;
1093 default:
1094 printf ("Row active to row active min %d ns\n", data[28]);
1095 break;
1096 }
1097
1098 switch (type) {
1099 case DDR2:
1100 printf ("RAS to CAS delay min %d.%02d ns\n",
1101 (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
1102 break;
1103 default:
1104 printf ("RAS to CAS delay min %d ns\n", data[29]);
1105 break;
1106 }
1107
1108 printf ("Minimum RAS pulse width %d ns\n", data[30]);
1109
1110 switch (type) {
1111 case DDR2:
1112 puts ("Density of each row ");
1113 decode_bits (data[31], decode_row_density_DDR2, 1);
1114 putc ('\n');
1115 break;
1116 default:
1117 puts ("Density of each row ");
1118 decode_bits (data[31], decode_row_density_default, 1);
1119 putc ('\n');
1120 break;
1121 }
1122
1123 switch (type) {
1124 case DDR2:
1125 puts ("Command and Address setup ");
1126 if (data[32] >= 0xA0) {
1127 printf ("1.%d%d ns\n",
1128 ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
1129 } else {
1130 printf ("0.%d%d ns\n",
1131 ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
1132 }
1133 break;
1134 default:
1135 printf ("Command and Address setup %c%d.%d ns\n",
1136 (data[32] & 0x80) ? '-' : '+',
1137 (data[32] >> 4) & 0x07, data[32] & 0x0F);
1138 break;
1139 }
1140
1141 switch (type) {
1142 case DDR2:
1143 puts ("Command and Address hold ");
1144 if (data[33] >= 0xA0) {
1145 printf ("1.%d%d ns\n",
1146 ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
1147 } else {
1148 printf ("0.%d%d ns\n",
1149 ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
1150 }
1151 break;
1152 default:
1153 printf ("Command and Address hold %c%d.%d ns\n",
1154 (data[33] & 0x80) ? '-' : '+',
1155 (data[33] >> 4) & 0x07, data[33] & 0x0F);
1156 break;
1157 }
1158
1159 switch (type) {
1160 case DDR2:
1161 printf ("Data signal input setup 0.%d%d ns\n",
1162 (data[34] >> 4) & 0x0F, data[34] & 0x0F);
1163 break;
1164 default:
1165 printf ("Data signal input setup %c%d.%d ns\n",
1166 (data[34] & 0x80) ? '-' : '+',
1167 (data[34] >> 4) & 0x07, data[34] & 0x0F);
1168 break;
1169 }
1170
1171 switch (type) {
1172 case DDR2:
1173 printf ("Data signal input hold 0.%d%d ns\n",
1174 (data[35] >> 4) & 0x0F, data[35] & 0x0F);
1175 break;
1176 default:
1177 printf ("Data signal input hold %c%d.%d ns\n",
1178 (data[35] & 0x80) ? '-' : '+',
1179 (data[35] >> 4) & 0x07, data[35] & 0x0F);
1180 break;
1181 }
1182
1183 puts ("Manufacturer's JEDEC ID ");
1184 for (j = 64; j <= 71; j++)
1185 printf ("%02X ", data[j]);
1186 putc ('\n');
1187 printf ("Manufacturing Location %02X\n", data[72]);
1188 puts ("Manufacturer's Part Number ");
1189 for (j = 73; j <= 90; j++)
1190 printf ("%02X ", data[j]);
1191 putc ('\n');
1192 printf ("Revision Code %02X %02X\n", data[91], data[92]);
1193 printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
1194 puts ("Assembly Serial Number ");
1195 for (j = 95; j <= 98; j++)
1196 printf ("%02X ", data[j]);
1197 putc ('\n');
1198
1199 if (DDR2 != type) {
1200 printf ("Speed rating PC%d\n",
1201 data[126] == 0x66 ? 66 : data[126]);
1202 }
1203 return 0;
1204 }
1205 #endif
1206
1207 int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1208 {
1209 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
1210 return 0;
1211 }
1212
1213 #if defined(CONFIG_I2C_MUX)
1214 int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1215 {
1216 int ret=0;
1217
1218 if (argc == 1) {
1219 /* show all busses */
1220 I2C_MUX *mux;
1221 I2C_MUX_DEVICE *device = i2c_mux_devices;
1222
1223 printf ("Busses reached over muxes:\n");
1224 while (device != NULL) {
1225 printf ("Bus ID: %x\n", device->busid);
1226 printf (" reached over Mux(es):\n");
1227 mux = device->mux;
1228 while (mux != NULL) {
1229 printf (" %s@%x ch: %x\n", mux->name, mux->chip, mux->channel);
1230 mux = mux->next;
1231 }
1232 device = device->next;
1233 }
1234 } else {
1235 I2C_MUX_DEVICE *dev;
1236
1237 dev = i2c_mux_ident_muxstring ((uchar *)argv[1]);
1238 ret = 0;
1239 }
1240 return ret;
1241 }
1242 #endif /* CONFIG_I2C_MUX */
1243
1244 #if defined(CONFIG_I2C_MULTI_BUS)
1245 int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1246 {
1247 int bus_idx, ret=0;
1248
1249 if (argc == 1)
1250 /* querying current setting */
1251 printf("Current bus is %d\n", i2c_get_bus_num());
1252 else {
1253 bus_idx = simple_strtoul(argv[1], NULL, 10);
1254 printf("Setting bus to %d\n", bus_idx);
1255 ret = i2c_set_bus_num(bus_idx);
1256 if (ret)
1257 printf("Failure changing bus number (%d)\n", ret);
1258 }
1259 return ret;
1260 }
1261 #endif /* CONFIG_I2C_MULTI_BUS */
1262
1263 int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1264 {
1265 int speed, ret=0;
1266
1267 if (argc == 1)
1268 /* querying current speed */
1269 printf("Current bus speed=%d\n", i2c_get_bus_speed());
1270 else {
1271 speed = simple_strtoul(argv[1], NULL, 10);
1272 printf("Setting bus speed to %d Hz\n", speed);
1273 ret = i2c_set_bus_speed(speed);
1274 if (ret)
1275 printf("Failure changing bus speed (%d)\n", ret);
1276 }
1277 return ret;
1278 }
1279
1280 int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1281 {
1282 #if defined(CONFIG_I2C_MUX)
1283 if (!strncmp(argv[1], "bu", 2))
1284 return do_i2c_add_bus(cmdtp, flag, --argc, ++argv);
1285 #endif /* CONFIG_I2C_MUX */
1286 if (!strncmp(argv[1], "sp", 2))
1287 return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv);
1288 #if defined(CONFIG_I2C_MULTI_BUS)
1289 if (!strncmp(argv[1], "de", 2))
1290 return do_i2c_bus_num(cmdtp, flag, --argc, ++argv);
1291 #endif /* CONFIG_I2C_MULTI_BUS */
1292 if (!strncmp(argv[1], "md", 2))
1293 return do_i2c_md(cmdtp, flag, --argc, ++argv);
1294 if (!strncmp(argv[1], "mm", 2))
1295 return do_i2c_mm(cmdtp, flag, --argc, ++argv);
1296 if (!strncmp(argv[1], "mw", 2))
1297 return do_i2c_mw(cmdtp, flag, --argc, ++argv);
1298 if (!strncmp(argv[1], "nm", 2))
1299 return do_i2c_nm(cmdtp, flag, --argc, ++argv);
1300 if (!strncmp(argv[1], "cr", 2))
1301 return do_i2c_crc(cmdtp, flag, --argc, ++argv);
1302 if (!strncmp(argv[1], "pr", 2))
1303 return do_i2c_probe(cmdtp, flag, --argc, ++argv);
1304 if (!strncmp(argv[1], "re", 2))
1305 return do_i2c_reset(cmdtp, flag, --argc, ++argv);
1306 if (!strncmp(argv[1], "lo", 2))
1307 return do_i2c_loop(cmdtp, flag, --argc, ++argv);
1308 #if defined(CONFIG_CMD_SDRAM)
1309 if (!strncmp(argv[1], "sd", 2))
1310 return do_sdram(cmdtp, flag, --argc, ++argv);
1311 #endif
1312 else
1313 cmd_usage(cmdtp);
1314 return 0;
1315 }
1316
1317 /***************************************************/
1318
1319 U_BOOT_CMD(
1320 i2c, 6, 1, do_i2c,
1321 "I2C sub-system",
1322 #if defined(CONFIG_I2C_MUX)
1323 "bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes.\n"
1324 #endif /* CONFIG_I2C_MUX */
1325 "speed [speed] - show or set I2C bus speed\n"
1326 #if defined(CONFIG_I2C_MULTI_BUS)
1327 "i2c dev [dev] - show or set current I2C bus\n"
1328 #endif /* CONFIG_I2C_MULTI_BUS */
1329 "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
1330 "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
1331 "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
1332 "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
1333 "i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
1334 "i2c probe - show devices on the I2C bus\n"
1335 "i2c reset - re-init the I2C Controller\n"
1336 "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
1337 #if defined(CONFIG_CMD_SDRAM)
1338 "i2c sdram chip - print SDRAM configuration information\n"
1339 #endif
1340 );
1341
1342 #if defined(CONFIG_I2C_MUX)
1343
1344 int i2c_mux_add_device(I2C_MUX_DEVICE *dev)
1345 {
1346 I2C_MUX_DEVICE *devtmp = i2c_mux_devices;
1347
1348 if (i2c_mux_devices == NULL) {
1349 i2c_mux_devices = dev;
1350 return 0;
1351 }
1352 while (devtmp->next != NULL)
1353 devtmp = devtmp->next;
1354
1355 devtmp->next = dev;
1356 return 0;
1357 }
1358
1359 I2C_MUX_DEVICE *i2c_mux_search_device(int id)
1360 {
1361 I2C_MUX_DEVICE *device = i2c_mux_devices;
1362
1363 while (device != NULL) {
1364 if (device->busid == id)
1365 return device;
1366 device = device->next;
1367 }
1368 return NULL;
1369 }
1370
1371 /* searches in the buf from *pos the next ':'.
1372 * returns:
1373 * 0 if found (with *pos = where)
1374 * < 0 if an error occured
1375 * > 0 if the end of buf is reached
1376 */
1377 static int i2c_mux_search_next (int *pos, uchar *buf, int len)
1378 {
1379 while ((buf[*pos] != ':') && (*pos < len)) {
1380 *pos += 1;
1381 }
1382 if (*pos >= len)
1383 return 1;
1384 if (buf[*pos] != ':')
1385 return -1;
1386 return 0;
1387 }
1388
1389 static int i2c_mux_get_busid (void)
1390 {
1391 int tmp = i2c_mux_busid;
1392
1393 i2c_mux_busid ++;
1394 return tmp;
1395 }
1396
1397 /* Analyses a Muxstring and sends immediately the
1398 Commands to the Muxes. Runs from Flash.
1399 */
1400 int i2c_mux_ident_muxstring_f (uchar *buf)
1401 {
1402 int pos = 0;
1403 int oldpos;
1404 int ret = 0;
1405 int len = strlen((char *)buf);
1406 int chip;
1407 uchar channel;
1408 int was = 0;
1409
1410 while (ret == 0) {
1411 oldpos = pos;
1412 /* search name */
1413 ret = i2c_mux_search_next(&pos, buf, len);
1414 if (ret != 0)
1415 printf ("ERROR\n");
1416 /* search address */
1417 pos ++;
1418 oldpos = pos;
1419 ret = i2c_mux_search_next(&pos, buf, len);
1420 if (ret != 0)
1421 printf ("ERROR\n");
1422 buf[pos] = 0;
1423 chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1424 buf[pos] = ':';
1425 /* search channel */
1426 pos ++;
1427 oldpos = pos;
1428 ret = i2c_mux_search_next(&pos, buf, len);
1429 if (ret < 0)
1430 printf ("ERROR\n");
1431 was = 0;
1432 if (buf[pos] != 0) {
1433 buf[pos] = 0;
1434 was = 1;
1435 }
1436 channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1437 if (was)
1438 buf[pos] = ':';
1439 if (i2c_write(chip, 0, 0, &channel, 1) != 0) {
1440 printf ("Error setting Mux: chip:%x channel: \
1441 %x\n", chip, channel);
1442 return -1;
1443 }
1444 pos ++;
1445 oldpos = pos;
1446
1447 }
1448
1449 return 0;
1450 }
1451
1452 /* Analyses a Muxstring and if this String is correct
1453 * adds a new I2C Bus.
1454 */
1455 I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf)
1456 {
1457 I2C_MUX_DEVICE *device;
1458 I2C_MUX *mux;
1459 int pos = 0;
1460 int oldpos;
1461 int ret = 0;
1462 int len = strlen((char *)buf);
1463 int was = 0;
1464
1465 device = (I2C_MUX_DEVICE *)malloc (sizeof(I2C_MUX_DEVICE));
1466 device->mux = NULL;
1467 device->busid = i2c_mux_get_busid ();
1468 device->next = NULL;
1469 while (ret == 0) {
1470 mux = (I2C_MUX *)malloc (sizeof(I2C_MUX));
1471 mux->next = NULL;
1472 /* search name of mux */
1473 oldpos = pos;
1474 ret = i2c_mux_search_next(&pos, buf, len);
1475 if (ret != 0)
1476 printf ("%s no name.\n", __FUNCTION__);
1477 mux->name = (char *)malloc (pos - oldpos + 1);
1478 memcpy (mux->name, &buf[oldpos], pos - oldpos);
1479 mux->name[pos - oldpos] = 0;
1480 /* search address */
1481 pos ++;
1482 oldpos = pos;
1483 ret = i2c_mux_search_next(&pos, buf, len);
1484 if (ret != 0)
1485 printf ("%s no mux address.\n", __FUNCTION__);
1486 buf[pos] = 0;
1487 mux->chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1488 buf[pos] = ':';
1489 /* search channel */
1490 pos ++;
1491 oldpos = pos;
1492 ret = i2c_mux_search_next(&pos, buf, len);
1493 if (ret < 0)
1494 printf ("%s no mux channel.\n", __FUNCTION__);
1495 was = 0;
1496 if (buf[pos] != 0) {
1497 buf[pos] = 0;
1498 was = 1;
1499 }
1500 mux->channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1501 if (was)
1502 buf[pos] = ':';
1503 if (device->mux == NULL)
1504 device->mux = mux;
1505 else {
1506 I2C_MUX *muxtmp = device->mux;
1507 while (muxtmp->next != NULL) {
1508 muxtmp = muxtmp->next;
1509 }
1510 muxtmp->next = mux;
1511 }
1512 pos ++;
1513 oldpos = pos;
1514 }
1515 if (ret > 0) {
1516 /* Add Device */
1517 i2c_mux_add_device (device);
1518 return device;
1519 }
1520
1521 return NULL;
1522 }
1523
1524 int i2x_mux_select_mux(int bus)
1525 {
1526 I2C_MUX_DEVICE *dev;
1527 I2C_MUX *mux;
1528
1529 if ((gd->flags & GD_FLG_RELOC) != GD_FLG_RELOC) {
1530 /* select Default Mux Bus */
1531 #if defined(CONFIG_SYS_I2C_IVM_BUS)
1532 i2c_mux_ident_muxstring_f ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
1533 #else
1534 {
1535 unsigned char *buf;
1536 buf = (unsigned char *) getenv("EEprom_ivm");
1537 if (buf != NULL)
1538 i2c_mux_ident_muxstring_f (buf);
1539 }
1540 #endif
1541 return 0;
1542 }
1543 dev = i2c_mux_search_device(bus);
1544 if (dev == NULL)
1545 return -1;
1546
1547 mux = dev->mux;
1548 while (mux != NULL) {
1549 if (i2c_write(mux->chip, 0, 0, &mux->channel, 1) != 0) {
1550 printf ("Error setting Mux: chip:%x channel: \
1551 %x\n", mux->chip, mux->channel);
1552 return -1;
1553 }
1554 mux = mux->next;
1555 }
1556 return 0;
1557 }
1558 #endif /* CONFIG_I2C_MUX */