]>
git.ipfire.org Git - people/ms/u-boot.git/blob - common/cmd_reginfo.c
3 * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #if defined(CONFIG_8xx)
28 #elif defined (CONFIG_405GP) || defined(CONFIG_405EP)
29 #include <asm/processor.h>
30 #elif defined (CONFIG_5xx)
32 #elif defined (CONFIG_MPC5200)
34 #elif defined (CONFIG_MPC86xx)
35 extern void mpc86xx_reginfo(void);
38 int do_reginfo (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
40 #if defined(CONFIG_8xx)
41 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
42 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
43 volatile sysconf8xx_t
*sysconf
= &immap
->im_siu_conf
;
44 volatile sit8xx_t
*timers
= &immap
->im_sit
;
46 /* Hopefully more PowerPC knowledgable people will add code to display
47 * other useful registers
50 printf ("\nSystem Configuration registers\n"
52 "\tIMMR\t0x%08X\n", get_immr(0));
54 printf("\tSIUMCR\t0x%08X", sysconf
->sc_siumcr
);
55 printf("\tSYPCR\t0x%08X\n",sysconf
->sc_sypcr
);
57 printf("\tSWT\t0x%08X", sysconf
->sc_swt
);
58 printf("\tSWSR\t0x%04X\n", sysconf
->sc_swsr
);
60 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
61 sysconf
->sc_sipend
, sysconf
->sc_simask
);
62 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
63 sysconf
->sc_siel
, sysconf
->sc_sivec
);
64 printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
65 sysconf
->sc_tesr
, sysconf
->sc_sdcr
);
67 printf ("Memory Controller Registers\n"
69 "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl
->memc_br0
, memctl
->memc_or0
);
70 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl
->memc_br1
, memctl
->memc_or1
);
71 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl
->memc_br2
, memctl
->memc_or2
);
72 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl
->memc_br3
, memctl
->memc_or3
);
73 printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl
->memc_br4
, memctl
->memc_or4
);
74 printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl
->memc_br5
, memctl
->memc_or5
);
75 printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl
->memc_br6
, memctl
->memc_or6
);
76 printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl
->memc_br7
, memctl
->memc_or7
);
78 "\tmamr\t0x%08X\tmbmr\t0x%08X \n",
79 memctl
->memc_mamr
, memctl
->memc_mbmr
);
80 printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
81 memctl
->memc_mstat
, memctl
->memc_mptpr
);
82 printf("\tmdr\t0x%08X \n", memctl
->memc_mdr
);
84 printf ("\nSystem Integration Timers\n"
85 "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
86 timers
->sit_tbscr
, timers
->sit_rtcsc
);
87 printf("\tPISCR\t0x%08X \n", timers
->sit_piscr
);
90 * May be some CPM info here?
93 #elif defined (CONFIG_405GP)
94 printf ("\n405GP registers; MSR=%08x\n",mfmsr());
95 printf ("\nUniversal Interrupt Controller Regs\n"
96 "uicsr uicsrs uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
98 "%08x %08x %08x %08x %08x %08x %08x %08x %08x\n",
109 puts ("\nMemory (SDRAM) Configuration\n"
110 "besra besrsa besrb besrsb bear mcopt1 rtr pmit\n");
112 mtdcr(memcfga
,mem_besra
); printf ("%08x ", mfdcr(memcfgd
));
113 mtdcr(memcfga
,mem_besrsa
); printf ("%08x ", mfdcr(memcfgd
));
114 mtdcr(memcfga
,mem_besrb
); printf ("%08x ", mfdcr(memcfgd
));
115 mtdcr(memcfga
,mem_besrsb
); printf ("%08x ", mfdcr(memcfgd
));
116 mtdcr(memcfga
,mem_bear
); printf ("%08x ", mfdcr(memcfgd
));
117 mtdcr(memcfga
,mem_mcopt1
); printf ("%08x ", mfdcr(memcfgd
));
118 mtdcr(memcfga
,mem_rtr
); printf ("%08x ", mfdcr(memcfgd
));
119 mtdcr(memcfga
,mem_pmit
); printf ("%08x ", mfdcr(memcfgd
));
122 "mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n");
123 mtdcr(memcfga
,mem_mb0cf
); printf ("%08x ", mfdcr(memcfgd
));
124 mtdcr(memcfga
,mem_mb1cf
); printf ("%08x ", mfdcr(memcfgd
));
125 mtdcr(memcfga
,mem_mb2cf
); printf ("%08x ", mfdcr(memcfgd
));
126 mtdcr(memcfga
,mem_mb3cf
); printf ("%08x ", mfdcr(memcfgd
));
127 mtdcr(memcfga
,mem_sdtr1
); printf ("%08x ", mfdcr(memcfgd
));
128 mtdcr(memcfga
,mem_ecccf
); printf ("%08x ", mfdcr(memcfgd
));
129 mtdcr(memcfga
,mem_eccerr
); printf ("%08x ", mfdcr(memcfgd
));
133 "dmasr dmasgc dmaadr\n"
135 "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n"
136 "%08x %08x %08x %08x %08x\n"
137 "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n"
138 "%08x %08x %08x %08x %08x\n",
139 mfdcr(dmasr
), mfdcr(dmasgc
),mfdcr(dmaadr
),
140 mfdcr(dmacr0
), mfdcr(dmact0
),mfdcr(dmada0
), mfdcr(dmasa0
), mfdcr(dmasb0
),
141 mfdcr(dmacr1
), mfdcr(dmact1
),mfdcr(dmada1
), mfdcr(dmasa1
), mfdcr(dmasb1
));
144 "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
145 "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
146 mfdcr(dmacr2
), mfdcr(dmact2
),mfdcr(dmada2
), mfdcr(dmasa2
), mfdcr(dmasb2
),
147 mfdcr(dmacr3
), mfdcr(dmact3
),mfdcr(dmada3
), mfdcr(dmasa3
), mfdcr(dmasb3
) );
151 "pbear pbesr0 pbesr1 epcr\n");
152 mtdcr(ebccfga
,pbear
); printf ("%08x ", mfdcr(ebccfgd
));
153 mtdcr(ebccfga
,pbesr0
); printf ("%08x ", mfdcr(ebccfgd
));
154 mtdcr(ebccfga
,pbesr1
); printf ("%08x ", mfdcr(ebccfgd
));
155 mtdcr(ebccfga
,epcr
); printf ("%08x ", mfdcr(ebccfgd
));
158 "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n");
159 mtdcr(ebccfga
,pb0cr
); printf ("%08x ", mfdcr(ebccfgd
));
160 mtdcr(ebccfga
,pb0ap
); printf ("%08x ", mfdcr(ebccfgd
));
161 mtdcr(ebccfga
,pb1cr
); printf ("%08x ", mfdcr(ebccfgd
));
162 mtdcr(ebccfga
,pb1ap
); printf ("%08x ", mfdcr(ebccfgd
));
163 mtdcr(ebccfga
,pb2cr
); printf ("%08x ", mfdcr(ebccfgd
));
164 mtdcr(ebccfga
,pb2ap
); printf ("%08x ", mfdcr(ebccfgd
));
165 mtdcr(ebccfga
,pb3cr
); printf ("%08x ", mfdcr(ebccfgd
));
166 mtdcr(ebccfga
,pb3ap
); printf ("%08x ", mfdcr(ebccfgd
));
169 "pb4cr pb4ap pb5cr bp5ap pb6cr pb6ap pb7cr pb7ap\n");
170 mtdcr(ebccfga
,pb4cr
); printf ("%08x ", mfdcr(ebccfgd
));
171 mtdcr(ebccfga
,pb4ap
); printf ("%08x ", mfdcr(ebccfgd
));
172 mtdcr(ebccfga
,pb5cr
); printf ("%08x ", mfdcr(ebccfgd
));
173 mtdcr(ebccfga
,pb5ap
); printf ("%08x ", mfdcr(ebccfgd
));
174 mtdcr(ebccfga
,pb6cr
); printf ("%08x ", mfdcr(ebccfgd
));
175 mtdcr(ebccfga
,pb6ap
); printf ("%08x ", mfdcr(ebccfgd
));
176 mtdcr(ebccfga
,pb7cr
); printf ("%08x ", mfdcr(ebccfgd
));
177 mtdcr(ebccfga
,pb7ap
); printf ("%08x ", mfdcr(ebccfgd
));
181 #elif defined(CONFIG_405EP)
182 printf ("\n405EP registers; MSR=%08x\n",mfmsr());
183 printf ("\nUniversal Interrupt Controller Regs\n"
184 "uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
186 "%08x %08x %08x %08x %08x %08x %08x %08x\n",
196 puts ("\nMemory (SDRAM) Configuration\n"
197 "mcopt1 rtr pmit mb0cf mb1cf sdtr1\n");
199 mtdcr(memcfga
,mem_mcopt1
); printf ("%08x ", mfdcr(memcfgd
));
200 mtdcr(memcfga
,mem_rtr
); printf ("%08x ", mfdcr(memcfgd
));
201 mtdcr(memcfga
,mem_pmit
); printf ("%08x ", mfdcr(memcfgd
));
202 mtdcr(memcfga
,mem_mb0cf
); printf ("%08x ", mfdcr(memcfgd
));
203 mtdcr(memcfga
,mem_mb1cf
); printf ("%08x ", mfdcr(memcfgd
));
204 mtdcr(memcfga
,mem_sdtr1
); printf ("%08x ", mfdcr(memcfgd
));
208 "dmasr dmasgc dmaadr\n" "%08x %08x %08x\n"
209 "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n"
210 "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n",
211 mfdcr(dmasr
), mfdcr(dmasgc
),mfdcr(dmaadr
),
212 mfdcr(dmacr0
), mfdcr(dmact0
),mfdcr(dmada0
), mfdcr(dmasa0
), mfdcr(dmasb0
),
213 mfdcr(dmacr1
), mfdcr(dmact1
),mfdcr(dmada1
), mfdcr(dmasa1
), mfdcr(dmasb1
));
216 "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
217 "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
218 mfdcr(dmacr2
), mfdcr(dmact2
),mfdcr(dmada2
), mfdcr(dmasa2
), mfdcr(dmasb2
),
219 mfdcr(dmacr3
), mfdcr(dmact3
),mfdcr(dmada3
), mfdcr(dmasa3
), mfdcr(dmasb3
) );
223 "pbear pbesr0 pbesr1 epcr\n");
224 mtdcr(ebccfga
,pbear
); printf ("%08x ", mfdcr(ebccfgd
));
225 mtdcr(ebccfga
,pbesr0
); printf ("%08x ", mfdcr(ebccfgd
));
226 mtdcr(ebccfga
,pbesr1
); printf ("%08x ", mfdcr(ebccfgd
));
227 mtdcr(ebccfga
,epcr
); printf ("%08x ", mfdcr(ebccfgd
));
230 "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n");
231 mtdcr(ebccfga
,pb0cr
); printf ("%08x ", mfdcr(ebccfgd
));
232 mtdcr(ebccfga
,pb0ap
); printf ("%08x ", mfdcr(ebccfgd
));
233 mtdcr(ebccfga
,pb1cr
); printf ("%08x ", mfdcr(ebccfgd
));
234 mtdcr(ebccfga
,pb1ap
); printf ("%08x ", mfdcr(ebccfgd
));
235 mtdcr(ebccfga
,pb2cr
); printf ("%08x ", mfdcr(ebccfgd
));
236 mtdcr(ebccfga
,pb2ap
); printf ("%08x ", mfdcr(ebccfgd
));
237 mtdcr(ebccfga
,pb3cr
); printf ("%08x ", mfdcr(ebccfgd
));
238 mtdcr(ebccfga
,pb3ap
); printf ("%08x ", mfdcr(ebccfgd
));
242 mtdcr(ebccfga
,pb4cr
); printf ("%08x ", mfdcr(ebccfgd
));
243 mtdcr(ebccfga
,pb4ap
); printf ("%08x ", mfdcr(ebccfgd
));
246 #elif defined(CONFIG_5xx)
248 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
249 volatile memctl5xx_t
*memctl
= &immap
->im_memctl
;
250 volatile sysconf5xx_t
*sysconf
= &immap
->im_siu_conf
;
251 volatile sit5xx_t
*timers
= &immap
->im_sit
;
252 volatile car5xx_t
*car
= &immap
->im_clkrst
;
253 volatile uimb5xx_t
*uimb
= &immap
->im_uimb
;
255 puts ("\nSystem Configuration registers\n");
256 printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf
->sc_siumcr
);
257 printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf
->sc_sypcr
, sysconf
->sc_swsr
);
258 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf
->sc_sipend
, sysconf
->sc_simask
);
259 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf
->sc_siel
, sysconf
->sc_sivec
);
260 printf("\tTESR\t0x%08X\n", sysconf
->sc_tesr
);
262 puts ("\nMemory Controller Registers\n");
263 printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl
->memc_br0
, memctl
->memc_or0
);
264 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl
->memc_br1
, memctl
->memc_or1
);
265 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl
->memc_br2
, memctl
->memc_or2
);
266 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl
->memc_br3
, memctl
->memc_or3
);
267 printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl
->memc_dmbr
, memctl
->memc_dmor
);
268 printf("\tMSTAT\t0x%08X\n", memctl
->memc_mstat
);
270 puts ("\nSystem Integration Timers\n");
271 printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers
->sit_tbscr
, timers
->sit_rtcsc
);
272 printf("\tPISCR\t0x%08X \n", timers
->sit_piscr
);
274 puts ("\nClocks and Reset\n");
275 printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car
->car_sccr
, car
->car_plprcr
);
277 puts ("\nU-Bus to IMB3 Bus Interface\n");
278 printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb
->uimb_umcr
, uimb
->uimb_uipend
);
281 #elif defined(CONFIG_MPC5200)
282 puts ("\nMPC5200 registers\n");
283 printf ("MBAR=%08x\n", CFG_MBAR
);
284 puts ("Memory map registers\n");
285 printf ("\tCS0: start %08X\tstop %08X\tconfig %08X\ten %d\n",
286 *(volatile ulong
*)MPC5XXX_CS0_START
,
287 *(volatile ulong
*)MPC5XXX_CS0_STOP
,
288 *(volatile ulong
*)MPC5XXX_CS0_CFG
,
289 (*(volatile ulong
*)MPC5XXX_ADDECR
& 0x00010000) ? 1 : 0);
290 printf ("\tCS1: start %08X\tstop %08X\tconfig %08X\ten %d\n",
291 *(volatile ulong
*)MPC5XXX_CS1_START
,
292 *(volatile ulong
*)MPC5XXX_CS1_STOP
,
293 *(volatile ulong
*)MPC5XXX_CS1_CFG
,
294 (*(volatile ulong
*)MPC5XXX_ADDECR
& 0x00020000) ? 1 : 0);
295 printf ("\tCS2: start %08X\tstop %08X\tconfig %08X\ten %d\n",
296 *(volatile ulong
*)MPC5XXX_CS2_START
,
297 *(volatile ulong
*)MPC5XXX_CS2_STOP
,
298 *(volatile ulong
*)MPC5XXX_CS2_CFG
,
299 (*(volatile ulong
*)MPC5XXX_ADDECR
& 0x00040000) ? 1 : 0);
300 printf ("\tCS3: start %08X\tstop %08X\tconfig %08X\ten %d\n",
301 *(volatile ulong
*)MPC5XXX_CS3_START
,
302 *(volatile ulong
*)MPC5XXX_CS3_STOP
,
303 *(volatile ulong
*)MPC5XXX_CS3_CFG
,
304 (*(volatile ulong
*)MPC5XXX_ADDECR
& 0x00080000) ? 1 : 0);
305 printf ("\tCS4: start %08X\tstop %08X\tconfig %08X\ten %d\n",
306 *(volatile ulong
*)MPC5XXX_CS4_START
,
307 *(volatile ulong
*)MPC5XXX_CS4_STOP
,
308 *(volatile ulong
*)MPC5XXX_CS4_CFG
,
309 (*(volatile ulong
*)MPC5XXX_ADDECR
& 0x00100000) ? 1 : 0);
310 printf ("\tCS5: start %08X\tstop %08X\tconfig %08X\ten %d\n",
311 *(volatile ulong
*)MPC5XXX_CS5_START
,
312 *(volatile ulong
*)MPC5XXX_CS5_STOP
,
313 *(volatile ulong
*)MPC5XXX_CS5_CFG
,
314 (*(volatile ulong
*)MPC5XXX_ADDECR
& 0x00200000) ? 1 : 0);
315 printf ("\tCS6: start %08X\tstop %08X\tconfig %08X\ten %d\n",
316 *(volatile ulong
*)MPC5XXX_CS6_START
,
317 *(volatile ulong
*)MPC5XXX_CS6_STOP
,
318 *(volatile ulong
*)MPC5XXX_CS6_CFG
,
319 (*(volatile ulong
*)MPC5XXX_ADDECR
& 0x04000000) ? 1 : 0);
320 printf ("\tCS7: start %08X\tstop %08X\tconfig %08X\ten %d\n",
321 *(volatile ulong
*)MPC5XXX_CS7_START
,
322 *(volatile ulong
*)MPC5XXX_CS7_STOP
,
323 *(volatile ulong
*)MPC5XXX_CS7_CFG
,
324 (*(volatile ulong
*)MPC5XXX_ADDECR
& 0x08000000) ? 1 : 0);
325 printf ("\tBOOTCS: start %08X\tstop %08X\tconfig %08X\ten %d\n",
326 *(volatile ulong
*)MPC5XXX_BOOTCS_START
,
327 *(volatile ulong
*)MPC5XXX_BOOTCS_STOP
,
328 *(volatile ulong
*)MPC5XXX_BOOTCS_CFG
,
329 (*(volatile ulong
*)MPC5XXX_ADDECR
& 0x02000000) ? 1 : 0);
330 printf ("\tSDRAMCS0: %08X\n",
331 *(volatile ulong
*)MPC5XXX_SDRAM_CS0CFG
);
332 printf ("\tSDRAMCS1: %08X\n",
333 *(volatile ulong
*)MPC5XXX_SDRAM_CS1CFG
);
334 #elif defined(CONFIG_MPC86xx)
336 #endif /* CONFIG_MPC86xx */
341 /**************************************************/
343 #if ( defined(CONFIG_8xx) || defined(CONFIG_405GP) || \
344 defined(CONFIG_405EP) || defined(CONFIG_MPC5200) || \
345 defined(CONFIG_MPC86xx)) && \
346 defined(CONFIG_CMD_REGINFO)
349 reginfo
, 2, 1, do_reginfo
,
350 "reginfo - print register information\n",