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git.ipfire.org Git - people/ms/u-boot.git/blob - common/miiphybb.c
8d18919a34c0cdd0c5bff76cb70823541ea01185
3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * This provides a bit-banged interface to the ethernet MII management
31 #include <ppc_asm.tmpl>
33 #ifdef CONFIG_BITBANGMII
36 /*****************************************************************************
38 * Utility to send the preamble, address, and register (common to read
41 static void miiphy_pre(char read
,
46 volatile ioport_t
*iop
= ioport_addr((immap_t
*)CFG_IMMR
, MDIO_PORT
);
49 * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
50 * The IEEE spec says this is a PHY optional requirement. The AMD
51 * 79C874 requires one after power up and one after a MII communications
52 * error. This means that we are doing more preambles than we need,
53 * but it is safer and will be much more robust.
58 for(j
= 0; j
< 32; j
++)
66 /* send the start bit (01) and the read opcode (10) or write (10) */
67 MDC(0); MDIO(0); MIIDELAY
; MDC(1); MIIDELAY
;
68 MDC(0); MDIO(1); MIIDELAY
; MDC(1); MIIDELAY
;
69 MDC(0); MDIO(read
); MIIDELAY
; MDC(1); MIIDELAY
;
70 MDC(0); MDIO(!read
); MIIDELAY
; MDC(1); MIIDELAY
;
72 /* send the PHY address */
73 for(j
= 0; j
< 5; j
++)
76 if((addr
& 0x10) == 0)
90 /* send the register address */
91 for(j
= 0; j
< 5; j
++)
110 /*****************************************************************************
112 * Read a MII PHY register.
117 int miiphy_read(unsigned char addr
,
119 unsigned short *value
)
121 short rdreg
; /* register working value */
123 volatile ioport_t
*iop
= ioport_addr((immap_t
*)CFG_IMMR
, MDIO_PORT
);
125 miiphy_pre(1, addr
, reg
);
127 /* tri-state our MDIO I/O pin so we can read */
134 /* check the turnaround bit: the PHY should be driving it to zero */
137 /* printf("PHY didn't drive TA low\n"); */
138 for(j
= 0; j
< 32; j
++)
151 /* read 16 bits of register data, MSB first */
153 for(j
= 0; j
< 16; j
++)
173 printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg
, addr
, *value
);
180 /*****************************************************************************
182 * Write a MII PHY register.
187 int miiphy_write(unsigned char addr
,
189 unsigned short value
)
192 volatile ioport_t
*iop
= ioport_addr((immap_t
*)CFG_IMMR
, MDIO_PORT
);
194 miiphy_pre(0, addr
, reg
);
196 /* send the turnaround (10) */
197 MDC(0); MDIO(1); MIIDELAY
; MDC(1); MIIDELAY
;
198 MDC(0); MDIO(0); MIIDELAY
; MDC(1); MIIDELAY
;
200 /* write 16 bits of register data, MSB first */
201 for(j
= 0; j
< 16; j
++)
204 if((value
& 0x00008000) == 0)
219 * Tri-state the MDIO line.
230 #endif /* CONFIG_BITBANGMII */