common/stratixII.c

   1 /*
   2  * (C) Copyright 2007
   3  * Eran Liberty, Extricom , eran.liberty@gmail.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  */
  24
  25 #include <common.h>             /* core U-Boot definitions */
  26 #include <altera.h>
  27
  28 int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
  29                            int isSerial, int isSecure);
  30 int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize);
  31
  32 /****************************************************************/
  33 /* Stratix II Generic Implementation                            */
  34 int StratixII_load (Altera_desc * desc, void *buf, size_t bsize)
  35 {
  36         int ret_val = FPGA_FAIL;
  37
  38         switch (desc->iface) {
  39         case passive_serial:
  40                 ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 1, 0);
  41                 break;
  42         case fast_passive_parallel:
  43                 ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 0);
  44                 break;
  45         case fast_passive_parallel_security:
  46                 ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 1);
  47                 break;
  48
  49                 /* Add new interface types here */
  50         default:
  51                 printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
  52                         desc->iface);
  53         }
  54         return ret_val;
  55 }
  56
  57 int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize)
  58 {
  59         int ret_val = FPGA_FAIL;
  60
  61         switch (desc->iface) {
  62         case passive_serial:
  63         case fast_passive_parallel:
  64         case fast_passive_parallel_security:
  65                 ret_val = StratixII_ps_fpp_dump (desc, buf, bsize);
  66                 break;
  67                 /* Add new interface types here */
  68         default:
  69                 printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
  70                         desc->iface);
  71         }
  72         return ret_val;
  73 }
  74
  75 int StratixII_info (Altera_desc * desc)
  76 {
  77         return FPGA_SUCCESS;
  78 }
  79
  80 int StratixII_reloc (Altera_desc * desc, ulong reloc_offset)
  81 {
  82         int i;
  83         uint32_t dest = (uint32_t) desc & 0xff000000;
  84
  85         /* we assume a relocated code and non relocated code has different upper 8 bits */
  86         if (dest != ((uint32_t) desc->iface_fns & 0xff000000)) {
  87                 desc->iface_fns =
  88                     (void *)((uint32_t) (desc->iface_fns) + reloc_offset);
  89         }
  90         for (i = 0; i < sizeof (altera_board_specific_func) / sizeof (void *);
  91              i++) {
  92                 if (dest !=
  93                     ((uint32_t) (((void **)(desc->iface_fns))[i]) & 0xff000000))
  94                 {
  95                         ((void **)(desc->iface_fns))[i] =
  96                             (void
  97                              *)(((uint32_t) (((void **)(desc->iface_fns))[i])) +
  98                                 reloc_offset);
  99                 }
 100         }
 101         return FPGA_SUCCESS;
 102 }
 103
 104 int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize)
 105 {
 106         printf ("Stratix II Fast Passive Parallel dump is not implemented\n");
 107         return FPGA_FAIL;
 108 }
 109
 110 int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
 111                            int isSerial, int isSecure)
 112 {
 113         altera_board_specific_func *fns;
 114         int cookie;
 115         int ret_val = FPGA_FAIL;
 116         int bytecount;
 117         char *buff = buf;
 118         int i;
 119
 120         if (!desc) {
 121                 printf ("%s(%d) Altera_desc missing\n", __FUNCTION__, __LINE__);
 122                 return FPGA_FAIL;
 123         }
 124         if (!buff) {
 125                 printf ("%s(%d) buffer is missing\n", __FUNCTION__, __LINE__);
 126                 return FPGA_FAIL;
 127         }
 128         if (!bsize) {
 129                 printf ("%s(%d) size is zero\n", __FUNCTION__, __LINE__);
 130                 return FPGA_FAIL;
 131         }
 132         if (!desc->iface_fns) {
 133                 printf
 134                     ("%s(%d) Altera_desc function interface table is missing\n",
 135                      __FUNCTION__, __LINE__);
 136                 return FPGA_FAIL;
 137         }
 138         fns = (altera_board_specific_func *) (desc->iface_fns);
 139         cookie = desc->cookie;
 140
 141         if (!
 142             (fns->config && fns->status && fns->done && fns->data
 143              && fns->abort)) {
 144                 printf
 145                     ("%s(%d) Missing some function in the function interface table\n",
 146                      __FUNCTION__, __LINE__);
 147                 return FPGA_FAIL;
 148         }
 149
 150         /* 1. give board specific a chance to do anything before we start */
 151         if (fns->pre) {
 152                 if ((ret_val = fns->pre (cookie)) < 0) {
 153                         return ret_val;
 154                 }
 155         }
 156
 157         /* from this point on we must fail gracfully by calling lower layer abort */
 158
 159         /* 2. Strat burn cycle by deasserting config for t_CFG and waiting t_CF2CK after reaserted */
 160         fns->config (0, 1, cookie);
 161         udelay (5);             /* nCONFIG low pulse width 2usec */
 162         fns->config (1, 1, cookie);
 163         udelay (100);           /* nCONFIG high to first rising edge on DCLK */
 164
 165         /* 3. Start the Data cycle with clk deasserted */
 166         bytecount = 0;
 167         fns->clk (0, 1, cookie);
 168
 169         printf ("loading to fpga    ");
 170         while (bytecount < bsize) {
 171                 /* 3.1 check stratix has not signaled us an error */
 172                 if (fns->status (cookie) != 1) {
 173                         printf
 174                             ("\n%s(%d) Stratix failed (byte transfered till failure 0x%x)\n",
 175                              __FUNCTION__, __LINE__, bytecount);
 176                         fns->abort (cookie);
 177                         return FPGA_FAIL;
 178                 }
 179                 if (isSerial) {
 180                         int i;
 181                         uint8_t data = buff[bytecount++];
 182                         for (i = 0; i < 8; i++) {
 183                                 /* 3.2(ps) put data on the bus */
 184                                 fns->data ((data >> i) & 1, 1, cookie);
 185
 186                                 /* 3.3(ps) clock once */
 187                                 fns->clk (1, 1, cookie);
 188                                 fns->clk (0, 1, cookie);
 189                         }
 190                 } else {
 191                         /* 3.2(fpp) put data on the bus */
 192                         fns->data (buff[bytecount++], 1, cookie);
 193
 194                         /* 3.3(fpp) clock once */
 195                         fns->clk (1, 1, cookie);
 196                         fns->clk (0, 1, cookie);
 197
 198                         /* 3.4(fpp) for secure cycle push 3 more  clocks */
 199                         for (i = 0; isSecure && i < 3; i++) {
 200                                 fns->clk (1, 1, cookie);
 201                                 fns->clk (0, 1, cookie);
 202                         }
 203                 }
 204
 205                 /* 3.5 while clk is deasserted it is safe to print some progress indication */
 206                 if ((bytecount % (bsize / 100)) == 0) {
 207                         printf ("\b\b\b%02d\%", bytecount * 100 / bsize);
 208                 }
 209         }
 210
 211         /* 4. Set one last clock and check conf done signal */
 212         fns->clk (1, 1, cookie);
 213         udelay (100);
 214         if (!fns->done (cookie)) {
 215                 printf (" error!.\n");
 216                 fns->abort (cookie);
 217                 return FPGA_FAIL;
 218         } else {
 219                 printf ("\b\b\b done.\n");
 220         }
 221
 222         /* 5. call lower layer post configuration */
 223         if (fns->post) {
 224                 if ((ret_val = fns->post (cookie)) < 0) {
 225                         fns->abort (cookie);
 226                         return ret_val;
 227                 }
 228         }
 229
 230         return FPGA_SUCCESS;
 231 }