3 * Eran Liberty, Extricom , eran.liberty@gmail.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <common.h> /* core U-Boot definitions */
28 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_STRATIX_II)
30 int StratixII_ps_fpp_load (Altera_desc
* desc
, void *buf
, size_t bsize
,
31 int isSerial
, int isSecure
);
32 int StratixII_ps_fpp_dump (Altera_desc
* desc
, void *buf
, size_t bsize
);
34 /****************************************************************/
35 /* Stratix II Generic Implementation */
36 int StratixII_load (Altera_desc
* desc
, void *buf
, size_t bsize
)
38 int ret_val
= FPGA_FAIL
;
40 switch (desc
->iface
) {
42 ret_val
= StratixII_ps_fpp_load (desc
, buf
, bsize
, 1, 0);
44 case fast_passive_parallel
:
45 ret_val
= StratixII_ps_fpp_load (desc
, buf
, bsize
, 0, 0);
47 case fast_passive_parallel_security
:
48 ret_val
= StratixII_ps_fpp_load (desc
, buf
, bsize
, 0, 1);
51 /* Add new interface types here */
53 printf ("%s: Unsupported interface type, %d\n", __FUNCTION__
,
59 int StratixII_dump (Altera_desc
* desc
, void *buf
, size_t bsize
)
61 int ret_val
= FPGA_FAIL
;
63 switch (desc
->iface
) {
65 case fast_passive_parallel
:
66 case fast_passive_parallel_security
:
67 ret_val
= StratixII_ps_fpp_dump (desc
, buf
, bsize
);
69 /* Add new interface types here */
71 printf ("%s: Unsupported interface type, %d\n", __FUNCTION__
,
77 int StratixII_info (Altera_desc
* desc
)
82 int StratixII_reloc (Altera_desc
* desc
, ulong reloc_offset
)
85 uint32_t dest
= (uint32_t) desc
& 0xff000000;
87 /* we assume a relocated code and non relocated code has different upper 8 bits */
88 if (dest
!= ((uint32_t) desc
->iface_fns
& 0xff000000)) {
90 (void *)((uint32_t) (desc
->iface_fns
) + reloc_offset
);
92 for (i
= 0; i
< sizeof (altera_board_specific_func
) / sizeof (void *);
95 ((uint32_t) (((void **)(desc
->iface_fns
))[i
]) & 0xff000000))
97 ((void **)(desc
->iface_fns
))[i
] =
99 *)(((uint32_t) (((void **)(desc
->iface_fns
))[i
])) +
106 int StratixII_ps_fpp_dump (Altera_desc
* desc
, void *buf
, size_t bsize
)
108 printf ("Stratix II Fast Passive Parallel dump is not implemented\n");
112 int StratixII_ps_fpp_load (Altera_desc
* desc
, void *buf
, size_t bsize
,
113 int isSerial
, int isSecure
)
115 altera_board_specific_func
*fns
;
117 int ret_val
= FPGA_FAIL
;
123 printf ("%s(%d) Altera_desc missing\n", __FUNCTION__
, __LINE__
);
127 printf ("%s(%d) buffer is missing\n", __FUNCTION__
, __LINE__
);
131 printf ("%s(%d) size is zero\n", __FUNCTION__
, __LINE__
);
134 if (!desc
->iface_fns
) {
136 ("%s(%d) Altera_desc function interface table is missing\n",
137 __FUNCTION__
, __LINE__
);
140 fns
= (altera_board_specific_func
*) (desc
->iface_fns
);
141 cookie
= desc
->cookie
;
144 (fns
->config
&& fns
->status
&& fns
->done
&& fns
->data
147 ("%s(%d) Missing some function in the function interface table\n",
148 __FUNCTION__
, __LINE__
);
152 /* 1. give board specific a chance to do anything before we start */
154 if ((ret_val
= fns
->pre (cookie
)) < 0) {
159 /* from this point on we must fail gracfully by calling lower layer abort */
161 /* 2. Strat burn cycle by deasserting config for t_CFG and waiting t_CF2CK after reaserted */
162 fns
->config (0, 1, cookie
);
163 udelay (5); /* nCONFIG low pulse width 2usec */
164 fns
->config (1, 1, cookie
);
165 udelay (100); /* nCONFIG high to first rising edge on DCLK */
167 /* 3. Start the Data cycle with clk deasserted */
169 fns
->clk (0, 1, cookie
);
171 printf ("loading to fpga ");
172 while (bytecount
< bsize
) {
173 /* 3.1 check stratix has not signaled us an error */
174 if (fns
->status (cookie
) != 1) {
176 ("\n%s(%d) Stratix failed (byte transfered till failure 0x%x)\n",
177 __FUNCTION__
, __LINE__
, bytecount
);
183 uint8_t data
= buff
[bytecount
++];
184 for (i
= 0; i
< 8; i
++) {
185 /* 3.2(ps) put data on the bus */
186 fns
->data ((data
>> i
) & 1, 1, cookie
);
188 /* 3.3(ps) clock once */
189 fns
->clk (1, 1, cookie
);
190 fns
->clk (0, 1, cookie
);
193 /* 3.2(fpp) put data on the bus */
194 fns
->data (buff
[bytecount
++], 1, cookie
);
196 /* 3.3(fpp) clock once */
197 fns
->clk (1, 1, cookie
);
198 fns
->clk (0, 1, cookie
);
200 /* 3.4(fpp) for secure cycle push 3 more clocks */
201 for (i
= 0; isSecure
&& i
< 3; i
++) {
202 fns
->clk (1, 1, cookie
);
203 fns
->clk (0, 1, cookie
);
207 /* 3.5 while clk is deasserted it is safe to print some progress indication */
208 if ((bytecount
% (bsize
/ 100)) == 0) {
209 printf ("\b\b\b%02d\%", bytecount
* 100 / bsize
);
213 /* 4. Set one last clock and check conf done signal */
214 fns
->clk (1, 1, cookie
);
216 if (!fns
->done (cookie
)) {
217 printf (" error!.\n");
221 printf ("\b\b\b done.\n");
224 /* 5. call lower layer post configuration */
226 if ((ret_val
= fns
->post (cookie
)) < 0) {
235 #endif /* defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_STRATIX_II) */