cpu/74xx_7xx/cpu.c

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * cpu.c
  26  *
  27  * CPU specific code
  28  *
  29  * written or collected and sometimes rewritten by
  30  * Magnus Damm <damm@bitsmart.com>
  31  *
  32  * minor modifications by
  33  * Wolfgang Denk <wd@denx.de>
  34  *
  35  * more modifications by
  36  * Josh Huber <huber@mclx.com>
  37  * added support for the 74xx series of cpus
  38  * added support for the 7xx series of cpus
  39  * made the code a little less hard-coded, and more auto-detectish
  40  */
  41
  42 #include <common.h>
  43 #include <command.h>
  44 #include <74xx_7xx.h>
  45 #include <asm/cache.h>
  46
  47 cpu_t
  48 get_cpu_type(void)
  49 {
  50         uint pvr = get_pvr();
  51         cpu_t type;
  52
  53         type = CPU_UNKNOWN;
  54
  55         switch (PVR_VER(pvr)) {
  56         case 0x000c:
  57                 type = CPU_7400;
  58                 break;
  59         case 0x0008:
  60                 type = CPU_750;
  61
  62                 if (((pvr >> 8) & 0xff) == 0x01) {
  63                         type = CPU_750CX;       /* old CX (80100 and 8010x?)*/
  64                 } else if (((pvr >> 8) & 0xff) == 0x22) {
  65                         type = CPU_750CX;       /* CX (82201,82202) and CXe (82214) */
  66                 } else if (((pvr >> 8) & 0xff) == 0x33) {
  67                         type = CPU_750CX;       /* CXe (83311) */
  68                 } else if (((pvr >> 12) & 0xF) == 0x3) {
  69                         type = CPU_755;
  70                 }
  71                 break;
  72
  73         case 0x800C:
  74                 type = CPU_7410;
  75                 break;
  76
  77         case 0x8000:
  78                 type = CPU_7450;
  79                 break;
  80
  81         default:
  82                 break;
  83         }
  84
  85         return type;
  86 }
  87
  88 /* ------------------------------------------------------------------------- */
  89
  90 #if !defined(CONFIG_BAB7xx)
  91 int checkcpu (void)
  92 {
  93         DECLARE_GLOBAL_DATA_PTR;
  94
  95         uint type   = get_cpu_type();
  96         uint pvr    = get_pvr();
  97         ulong clock = gd->cpu_clk;
  98         char buf[32];
  99         char *str;
 100
 101         puts ("CPU:   ");
 102
 103         switch (type) {
 104         case CPU_750CX:
 105                 printf ("750CX%s v%d.%d", (pvr&0xf0)?"e":"",
 106                         (pvr>>8) & 0xf,
 107                         pvr & 0xf);
 108                 goto    PR_CLK;
 109
 110         case CPU_750:
 111                 str = "750";
 112                 break;
 113
 114         case CPU_755:
 115                 str = "755";
 116                 break;
 117
 118         case CPU_7400:
 119                 str = "MPC7400";
 120                 break;
 121
 122         case CPU_7410:
 123                 str = "MPC7410";
 124                 break;
 125
 126         case CPU_7450:
 127                 str = "MPC7450";
 128                 break;
 129
 130         default:
 131                 printf("Unknown CPU -- PVR: 0x%08x\n", pvr);
 132                 return -1;
 133         }
 134
 135         printf ("%s v%d.%d", str, (pvr >> 8) & 0xFF, pvr & 0xFF);
 136 PR_CLK:
 137         printf (" @ %s MHz\n", strmhz(buf, clock));
 138
 139         return (0);
 140 }
 141 #endif
 142 /* these two functions are unimplemented currently [josh] */
 143
 144 /* ------------------------------------------------------------------------- */
 145 /* L1 i-cache                                                                */
 146
 147 int
 148 checkicache(void)
 149 {
 150         return 0; /* XXX */
 151 }
 152
 153 /* ------------------------------------------------------------------------- */
 154 /* L1 d-cache                                                                */
 155
 156 int
 157 checkdcache(void)
 158 {
 159         return 0; /* XXX */
 160 }
 161
 162 /* ------------------------------------------------------------------------- */
 163
 164 static inline void
 165 soft_restart(unsigned long addr)
 166 {
 167         /* SRR0 has system reset vector, SRR1 has default MSR value */
 168         /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
 169
 170         __asm__ __volatile__ ("mtspr    26, %0"         :: "r" (addr));
 171         __asm__ __volatile__ ("li       4, (1 << 6)"    ::: "r4");
 172         __asm__ __volatile__ ("mtspr    27, 4");
 173         __asm__ __volatile__ ("rfi");
 174
 175         while(1);       /* not reached */
 176 }
 177
 178
 179 #if !defined(CONFIG_PCIPPC2) && \
 180     !defined(CONFIG_BAB7xx)  && \
 181     !defined(CONFIG_ELPPC)
 182 /* no generic way to do board reset. simply call soft_reset. */
 183 void
 184 do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 185 {
 186         ulong addr;
 187         /* flush and disable I/D cache */
 188         __asm__ __volatile__ ("mfspr    3, 1008"        ::: "r3");
 189         __asm__ __volatile__ ("ori      5, 5, 0xcc00"   ::: "r5");
 190         __asm__ __volatile__ ("ori      4, 3, 0xc00"    ::: "r4");
 191         __asm__ __volatile__ ("andc     5, 3, 5"        ::: "r5");
 192         __asm__ __volatile__ ("sync");
 193         __asm__ __volatile__ ("mtspr    1008, 4");
 194         __asm__ __volatile__ ("isync");
 195         __asm__ __volatile__ ("sync");
 196         __asm__ __volatile__ ("mtspr    1008, 5");
 197         __asm__ __volatile__ ("isync");
 198         __asm__ __volatile__ ("sync");
 199
 200 #ifdef CFG_RESET_ADDRESS
 201         addr = CFG_RESET_ADDRESS;
 202 #else
 203         /*
 204          * note: when CFG_MONITOR_BASE points to a RAM address,
 205          * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
 206          * address. Better pick an address known to be invalid on your
 207          * system and assign it to CFG_RESET_ADDRESS.
 208          */
 209         addr = CFG_MONITOR_BASE - sizeof (ulong);
 210 #endif
 211         soft_restart(addr);
 212         while(1);       /* not reached */
 213 }
 214 #endif
 215
 216 /* ------------------------------------------------------------------------- */
 217
 218 /*
 219  * For the 7400 the TB clock runs at 1/4 the cpu bus speed.
 220  */
 221 unsigned long
 222 get_tbclk (void)
 223 {
 224         return CFG_BUS_HZ / 4;
 225 }
 226
 227 /* ------------------------------------------------------------------------- */
 228
 229 #if defined(CONFIG_WATCHDOG)
 230 #if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx)
 231 void
 232 watchdog_reset(void)
 233 {
 234
 235 }
 236 #endif  /* !CONFIG_PCIPPC2 && !CONFIG_BAB7xx */
 237 #endif  /* CONFIG_WATCHDOG */
 238
 239 /* ------------------------------------------------------------------------- */