]>
git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/74xx_7xx/cpu.c
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
35 * more modifications by
36 * Josh Huber <huber@mclx.com>
37 * added support for the 74xx series of cpus
38 * added support for the 7xx series of cpus
39 * made the code a little less hard-coded, and more auto-detectish
45 #include <asm/cache.h>
47 #ifdef CONFIG_AMIGAONEG3SE
48 #include "../board/MAI/AmigaOneG3SE/via686.h"
49 #include "../board/MAI/AmigaOneG3SE/memio.h"
60 switch (PVR_VER(pvr
)) {
67 if (((pvr
>> 8) & 0xff) == 0x01) {
68 type
= CPU_750CX
; /* old CX (80100 and 8010x?)*/
69 } else if (((pvr
>> 8) & 0xff) == 0x22) {
70 type
= CPU_750CX
; /* CX (82201,82202) and CXe (82214) */
71 } else if (((pvr
>> 8) & 0xff) == 0x33) {
72 type
= CPU_750CX
; /* CXe (83311) */
73 } else if (((pvr
>> 12) & 0xF) == 0x3) {
97 /* ------------------------------------------------------------------------- */
99 #if !defined(CONFIG_BAB7xx)
102 DECLARE_GLOBAL_DATA_PTR
;
104 uint type
= get_cpu_type();
105 uint pvr
= get_pvr();
106 ulong clock
= gd
->cpu_clk
;
114 printf ("750CX%s v%d.%d", (pvr
&0xf0)?"e":"",
144 printf("Unknown CPU -- PVR: 0x%08x\n", pvr
);
148 printf ("%s v%d.%d", str
, (pvr
>> 8) & 0xFF, pvr
& 0xFF);
150 printf (" @ %s MHz\n", strmhz(buf
, clock
));
155 /* these two functions are unimplemented currently [josh] */
157 /* -------------------------------------------------------------------- */
166 /* -------------------------------------------------------------------- */
175 /* -------------------------------------------------------------------- */
178 soft_restart(unsigned long addr
)
180 /* SRR0 has system reset vector, SRR1 has default MSR value */
181 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
183 __asm__
__volatile__ ("mtspr 26, %0" :: "r" (addr
));
184 __asm__
__volatile__ ("li 4, (1 << 6)" ::: "r4");
185 __asm__
__volatile__ ("mtspr 27, 4");
186 __asm__
__volatile__ ("rfi");
188 while(1); /* not reached */
192 #if !defined(CONFIG_PCIPPC2) && \
193 !defined(CONFIG_BAB7xx) && \
194 !defined(CONFIG_ELPPC)
195 /* no generic way to do board reset. simply call soft_reset. */
197 do_reset (cmd_tbl_t
*cmdtp
, bd_t
*bd
, int flag
, int argc
, char *argv
[])
200 /* flush and disable I/D cache */
201 __asm__
__volatile__ ("mfspr 3, 1008" ::: "r3");
202 __asm__
__volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
203 __asm__
__volatile__ ("ori 4, 3, 0xc00" ::: "r4");
204 __asm__
__volatile__ ("andc 5, 3, 5" ::: "r5");
205 __asm__
__volatile__ ("sync");
206 __asm__
__volatile__ ("mtspr 1008, 4");
207 __asm__
__volatile__ ("isync");
208 __asm__
__volatile__ ("sync");
209 __asm__
__volatile__ ("mtspr 1008, 5");
210 __asm__
__volatile__ ("isync");
211 __asm__
__volatile__ ("sync");
213 #ifdef CFG_RESET_ADDRESS
214 addr
= CFG_RESET_ADDRESS
;
217 * note: when CFG_MONITOR_BASE points to a RAM address,
218 * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
219 * address. Better pick an address known to be invalid on your
220 * system and assign it to CFG_RESET_ADDRESS.
222 addr
= CFG_MONITOR_BASE
- sizeof (ulong
);
225 while(1); /* not reached */
229 /* ------------------------------------------------------------------------- */
232 * For the 7400 the TB clock runs at 1/4 the cpu bus speed.
234 #ifdef CONFIG_AMIGAONEG3SE
235 unsigned long get_tbclk(void)
237 DECLARE_GLOBAL_DATA_PTR
;
239 return (gd
->bus_clk
/ 4);
241 #else /* ! CONFIG_AMIGAONEG3SE */
243 unsigned long get_tbclk (void)
245 return CFG_BUS_HZ
/ 4;
247 #endif /* CONFIG_AMIGAONEG3SE */
248 /* ------------------------------------------------------------------------- */
250 #if defined(CONFIG_WATCHDOG)
251 #if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx)
257 #endif /* !CONFIG_PCIPPC2 && !CONFIG_BAB7xx */
258 #endif /* CONFIG_WATCHDOG */
260 /* ------------------------------------------------------------------------- */