cpu/arm1136/cpu.c

   1 /*
   2  * (C) Copyright 2004 Texas Insturments
   3  *
   4  * (C) Copyright 2002
   5  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   6  * Marius Groeger <mgroeger@sysgo.de>
   7  *
   8  * (C) Copyright 2002
   9  * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /*
  31  * CPU specific code
  32  */
  33
  34 #include <common.h>
  35 #include <command.h>
  36 #if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
  37 #include <asm/arch/omap2420.h>
  38 #endif
  39
  40 #ifdef CONFIG_USE_IRQ
  41 DECLARE_GLOBAL_DATA_PTR;
  42 #endif
  43
  44 /* read co-processor 15, register #1 (control register) */
  45 static unsigned long read_p15_c1 (void)
  46 {
  47         unsigned long value;
  48
  49         __asm__ __volatile__(
  50                                                 "mrc    p15, 0, %0, c1, c0, 0   @ read control reg\n"
  51                                                 : "=r" (value)
  52                                                 :
  53                                                 : "memory");
  54         return value;
  55 }
  56
  57 /* write to co-processor 15, register #1 (control register) */
  58 static void write_p15_c1 (unsigned long value)
  59 {
  60         __asm__ __volatile__(
  61                                                 "mcr    p15, 0, %0, c1, c0, 0   @ write it back\n"
  62                                                 :
  63                                                 : "r" (value)
  64                                                 : "memory");
  65
  66         read_p15_c1 ();
  67 }
  68
  69 static void cp_delay (void)
  70 {
  71         volatile int i;
  72
  73         /* Many OMAP regs need at least 2 nops  */
  74         for (i = 0; i < 100; i++);
  75 }
  76
  77 /* See also ARM Ref. Man. */
  78 #define C1_MMU          (1<<0)          /* mmu off/on */
  79 #define C1_ALIGN        (1<<1)          /* alignment faults off/on */
  80 #define C1_DC           (1<<2)          /* dcache off/on */
  81 #define C1_WB           (1<<3)          /* merging write buffer on/off */
  82 #define C1_BIG_ENDIAN   (1<<7)  /* big endian off/on */
  83 #define C1_SYS_PROT     (1<<8)          /* system protection */
  84 #define C1_ROM_PROT     (1<<9)          /* ROM protection */
  85 #define C1_IC           (1<<12)         /* icache off/on */
  86 #define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
  87 #define RESERVED_1      (0xf << 3)      /* must be 111b for R/W */
  88
  89 int cpu_init (void)
  90 {
  91         /*
  92          * setup up stacks if necessary
  93          */
  94 #ifdef CONFIG_USE_IRQ
  95         IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
  96         FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
  97 #endif
  98         return 0;
  99 }
 100
 101 int cleanup_before_linux (void)
 102 {
 103         /*
 104          * this function is called just before we call linux
 105          * it prepares the processor for linux
 106          *
 107          * we turn off caches etc ...
 108          */
 109
 110         unsigned long i;
 111
 112         disable_interrupts ();
 113
 114 #ifdef CONFIG_LCD
 115         {
 116                 extern void lcd_disable(void);
 117                 extern void lcd_panel_disable(void);
 118
 119                 lcd_disable(); /* proper disable of lcd & panel */
 120                 lcd_panel_disable();
 121         }
 122 #endif
 123
 124         /* turn off I/D-cache */
 125         asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 126         i &= ~(C1_DC | C1_IC);
 127         asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 128
 129         /* flush I/D-cache */
 130         i = 0;
 131         asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
 132         asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
 133         return(0);
 134 }
 135
 136 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 137 {
 138         disable_interrupts ();
 139         reset_cpu (0);
 140         /*NOTREACHED*/
 141         return(0);
 142 }
 143
 144 void icache_enable (void)
 145 {
 146         ulong reg;
 147
 148         reg = read_p15_c1 ();   /* get control reg. */
 149         cp_delay ();
 150         write_p15_c1 (reg | C1_IC);
 151 }
 152
 153 void icache_disable (void)
 154 {
 155         ulong reg;
 156
 157         reg = read_p15_c1 ();
 158         cp_delay ();
 159         write_p15_c1 (reg & ~C1_IC);
 160 }
 161
 162 int icache_status (void)
 163 {
 164         return(read_p15_c1 () & C1_IC) != 0;
 165 }