cpu/arm720t/interrupts.c

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  *
   6  * (C) Copyright 2002
   7  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   8  * Alex Zuepke <azu@sysgo.de>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <clps7111.h>
  31 #include <asm/proc-armv/ptrace.h>
  32 #include <asm/hardware.h>
  33
  34 #ifndef CONFIG_NETARM
  35 /* we always count down the max. */
  36 #define TIMER_LOAD_VAL 0xffff
  37 /* macro to read the 16 bit timer */
  38 #define READ_TIMER (IO_TC1D & 0xffff)
  39 #else
  40 #define IRQEN   (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
  41 #define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
  42 #define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
  43 #define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
  44 #define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
  45 #endif
  46
  47 #ifdef CONFIG_S3C4510B
  48 /* require interrupts for the S3C4510B */
  49 # ifndef CONFIG_USE_IRQ
  50 #  error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
  51 # else
  52 static struct _irq_handler IRQ_HANDLER[N_IRQS];
  53 # endif
  54 #endif  /* CONFIG_S3C4510B */
  55
  56 #ifdef CONFIG_USE_IRQ
  57 /* enable IRQ/FIQ interrupts */
  58 void enable_interrupts (void)
  59 {
  60         unsigned long temp;
  61         __asm__ __volatile__("mrs %0, cpsr\n"
  62                              "bic %0, %0, #0x80\n"
  63                              "msr cpsr_c, %0"
  64                              : "=r" (temp)
  65                              :
  66                              : "memory");
  67 }
  68
  69
  70 /*
  71  * disable IRQ/FIQ interrupts
  72  * returns true if interrupts had been enabled before we disabled them
  73  */
  74 int disable_interrupts (void)
  75 {
  76         unsigned long old,temp;
  77         __asm__ __volatile__("mrs %0, cpsr\n"
  78                              "orr %1, %0, #0x80\n"
  79                              "msr cpsr_c, %1"
  80                              : "=r" (old), "=r" (temp)
  81                              :
  82                              : "memory");
  83         return (old & 0x80) == 0;
  84 }
  85 #else /* CONFIG_USE_IRQ */
  86 void enable_interrupts (void)
  87 {
  88         return;
  89 }
  90 int disable_interrupts (void)
  91 {
  92         return 0;
  93 }
  94 #endif
  95
  96 void bad_mode (void)
  97 {
  98         panic ("Resetting CPU ...\n");
  99         reset_cpu (0);
 100 }
 101
 102 void show_regs (struct pt_regs *regs)
 103 {
 104         unsigned long flags;
 105         const char *processor_modes[] =
 106                 { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26",
 107 "UK6_26", "UK7_26",
 108                 "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26",
 109                                 "UK14_26", "UK15_26",
 110                 "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32",
 111                                 "UK6_32", "ABT_32",
 112                 "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32",
 113                                 "UK14_32", "SYS_32"
 114         };
 115
 116         flags = condition_codes (regs);
 117
 118         printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
 119                         "sp : %08lx  ip : %08lx  fp : %08lx\n",
 120                         instruction_pointer (regs),
 121                         regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
 122         printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
 123                         regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
 124         printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
 125                         regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
 126         printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
 127                         regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
 128         printf ("Flags: %c%c%c%c",
 129                         flags & CC_N_BIT ? 'N' : 'n',
 130                         flags & CC_Z_BIT ? 'Z' : 'z',
 131                         flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
 132         printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
 133                         interrupts_enabled (regs) ? "on" : "off",
 134                         fast_interrupts_enabled (regs) ? "on" : "off",
 135                         processor_modes[processor_mode (regs)],
 136                         thumb_mode (regs) ? " (T)" : "");
 137 }
 138
 139 void do_undefined_instruction (struct pt_regs *pt_regs)
 140 {
 141         printf ("undefined instruction\n");
 142         show_regs (pt_regs);
 143         bad_mode ();
 144 }
 145
 146 void do_software_interrupt (struct pt_regs *pt_regs)
 147 {
 148         printf ("software interrupt\n");
 149         show_regs (pt_regs);
 150         bad_mode ();
 151 }
 152
 153 void do_prefetch_abort (struct pt_regs *pt_regs)
 154 {
 155         printf ("prefetch abort\n");
 156         show_regs (pt_regs);
 157         bad_mode ();
 158 }
 159
 160 void do_data_abort (struct pt_regs *pt_regs)
 161 {
 162         printf ("data abort\n");
 163         show_regs (pt_regs);
 164         bad_mode ();
 165 }
 166
 167 void do_not_used (struct pt_regs *pt_regs)
 168 {
 169         printf ("not used\n");
 170         show_regs (pt_regs);
 171         bad_mode ();
 172 }
 173
 174 void do_fiq (struct pt_regs *pt_regs)
 175 {
 176         printf ("fast interrupt request\n");
 177         show_regs (pt_regs);
 178         bad_mode ();
 179 }
 180
 181 void do_irq (struct pt_regs *pt_regs)
 182 {
 183 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
 184         printf ("interrupt request\n");
 185         show_regs (pt_regs);
 186         bad_mode ();
 187 #elif defined(CONFIG_S3C4510B)
 188         unsigned int pending;
 189
 190         while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) {  /* sentinal value for no pending interrutps */
 191                 IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
 192
 193                 /* clear pending interrupt */
 194                 PUT_REG( REG_INTPEND, (1<<(pending>>2)));
 195         }
 196 #else
 197 #error do_irq() not defined for this CPU type
 198 #endif
 199 }
 200
 201
 202 #ifdef CONFIG_S3C4510B
 203 static void default_isr( void *data) {
 204         printf ("default_isr():  called for IRQ %d\n", (int)data);
 205 }
 206
 207 static void timer_isr( void *data) {
 208         unsigned int *pTime = (unsigned int *)data;
 209
 210         (*pTime)++;
 211         if ( !(*pTime % (CFG_HZ/4))) {
 212                 /* toggle LED 0 */
 213                 PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
 214         }
 215
 216 }
 217 #endif
 218
 219 static ulong timestamp;
 220 static ulong lastdec;
 221
 222 int interrupt_init (void)
 223 {
 224
 225 #if defined(CONFIG_NETARM)
 226         /* disable all interrupts */
 227         IRQEN = 0;
 228
 229         /* operate timer 2 in non-prescale mode */
 230         TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) |
 231                     NETARM_GEN_TCTL_ENABLE |
 232                     NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
 233
 234         /* set timer 2 counter */
 235         lastdec = TIMER_LOAD_VAL;
 236 #elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
 237         /* disable all interrupts */
 238         IO_INTMR1 = 0;
 239
 240         /* operate timer 1 in prescale mode */
 241         IO_SYSCON1 |= SYSCON1_TC1M;
 242
 243         /* select 2kHz clock source for timer 1 */
 244         IO_SYSCON1 &= ~SYSCON1_TC1S;
 245
 246         /* set timer 1 counter */
 247         lastdec = IO_TC1D = TIMER_LOAD_VAL;
 248 #elif defined(CONFIG_S3C4510B)
 249         int i;
 250
 251         /* install default interrupt handlers */
 252         for ( i = 0; i < N_IRQS; i++) {
 253                 IRQ_HANDLER[i].m_data = (void *)i;
 254                 IRQ_HANDLER[i].m_func = default_isr;
 255         }
 256
 257         /* configure interrupts for IRQ mode */
 258         PUT_REG( REG_INTMODE, 0x0);
 259         /* clear any pending interrupts */
 260         PUT_REG( REG_INTPEND, 0x1FFFFF);
 261
 262         lastdec = 0;
 263
 264         /* install interrupt handler for timer */
 265         IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
 266         IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
 267
 268         /* configure free running timer 0 */
 269         PUT_REG( REG_TMOD, 0x0);
 270         /* Stop timer 0 */
 271         CLR_REG( REG_TMOD, TM0_RUN);
 272
 273         /* Configure for interval mode */
 274         CLR_REG( REG_TMOD, TM1_TOGGLE);
 275
 276         /*
 277          * Load Timer data register with count down value.
 278          * count_down_val = CFG_SYS_CLK_FREQ/CFG_HZ
 279          */
 280         PUT_REG( REG_TDATA0, (CFG_SYS_CLK_FREQ / CFG_HZ));
 281
 282         /*
 283          * Enable global interrupt
 284          * Enable timer0 interrupt
 285          */
 286         CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
 287
 288         /* Start timer */
 289         SET_REG( REG_TMOD, TM0_RUN);
 290
 291 #else
 292 #error No interrupt_init() defined for this CPU type
 293 #endif
 294         timestamp = 0;
 295
 296         return (0);
 297 }
 298
 299 /*
 300  * timer without interrupts
 301  */
 302
 303
 304 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
 305
 306 void reset_timer (void)
 307 {
 308         reset_timer_masked ();
 309 }
 310
 311 ulong get_timer (ulong base)
 312 {
 313         return get_timer_masked () - base;
 314 }
 315
 316 void set_timer (ulong t)
 317 {
 318         timestamp = t;
 319 }
 320
 321 void udelay (unsigned long usec)
 322 {
 323         ulong tmo;
 324
 325         tmo = usec / 1000;
 326         tmo *= CFG_HZ;
 327         tmo /= 1000;
 328
 329         tmo += get_timer (0);
 330
 331         while (get_timer_masked () < tmo)
 332                 /*NOP*/;
 333 }
 334
 335 void reset_timer_masked (void)
 336 {
 337         /* reset time */
 338         lastdec = READ_TIMER;
 339         timestamp = 0;
 340 }
 341
 342 ulong get_timer_masked (void)
 343 {
 344         ulong now = READ_TIMER;
 345
 346         if (lastdec >= now) {
 347                 /* normal mode */
 348                 timestamp += lastdec - now;
 349         } else {
 350                 /* we have an overflow ... */
 351                 timestamp += lastdec + TIMER_LOAD_VAL - now;
 352         }
 353         lastdec = now;
 354
 355         return timestamp;
 356 }
 357
 358 void udelay_masked (unsigned long usec)
 359 {
 360         ulong tmo;
 361         ulong endtime;
 362         signed long diff;
 363
 364         if (usec >= 1000) {
 365                 tmo = usec / 1000;
 366                 tmo *= CFG_HZ;
 367                 tmo /= 1000;
 368         } else {
 369                 tmo = usec * CFG_HZ;
 370                 tmo /= (1000*1000);
 371         }
 372
 373         endtime = get_timer_masked () + tmo;
 374
 375         do {
 376                 ulong now = get_timer_masked ();
 377                 diff = endtime - now;
 378         } while (diff >= 0);
 379 }
 380
 381 #elif defined(CONFIG_S3C4510B)
 382
 383 ulong get_timer (ulong base)
 384 {
 385         return timestamp - base;
 386 }
 387
 388 void udelay (unsigned long usec)
 389 {
 390         u32 ticks;
 391
 392         ticks = (usec * CFG_HZ) / 1000000;
 393
 394         ticks += get_timer (0);
 395
 396         while (get_timer (0) < ticks)
 397                 /*NOP*/;
 398
 399 }
 400
 401 #else
 402 #error Timer routines not defined for this CPU type
 403 #endif