cpu/arm920t/start.S

   1 /*
   2  *  armboot - Startup Code for ARM920 CPU-core
   3  *
   4  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   5  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
   6  *  Copyright (c) 2002  Gary Jennejohn <gj@denx.de>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27
  28 #include <config.h>
  29 #include <version.h>
  30
  31
  32 /*
  33  *************************************************************************
  34  *
  35  * Jump vector table as in table 3.1 in [1]
  36  *
  37  *************************************************************************
  38  */
  39
  40
  41 .globl _start
  42 _start: b       reset
  43         ldr     pc, _undefined_instruction
  44         ldr     pc, _software_interrupt
  45         ldr     pc, _prefetch_abort
  46         ldr     pc, _data_abort
  47         ldr     pc, _not_used
  48         ldr     pc, _irq
  49         ldr     pc, _fiq
  50
  51 _undefined_instruction: .word undefined_instruction
  52 _software_interrupt:    .word software_interrupt
  53 _prefetch_abort:        .word prefetch_abort
  54 _data_abort:            .word data_abort
  55 _not_used:              .word not_used
  56 _irq:                   .word irq
  57 _fiq:                   .word fiq
  58
  59         .balignl 16,0xdeadbeef
  60
  61
  62 /*
  63  *************************************************************************
  64  *
  65  * Startup Code (reset vector)
  66  *
  67  * do important init only if we don't start from memory!
  68  * relocate armboot to ram
  69  * setup stack
  70  * jump to second stage
  71  *
  72  *************************************************************************
  73  */
  74
  75 _TEXT_BASE:
  76         .word   TEXT_BASE
  77
  78 .globl _armboot_start
  79 _armboot_start:
  80         .word _start
  81
  82 /*
  83  * Note: _armboot_end_data and _armboot_end are defined
  84  * by the (board-dependent) linker script.
  85  * _armboot_end_data is the first usable FLASH address after armboot
  86  */
  87 .globl _armboot_end_data
  88 _armboot_end_data:
  89         .word armboot_end_data
  90 .globl _armboot_end
  91 _armboot_end:
  92         .word armboot_end
  93
  94 #ifdef CONFIG_USE_IRQ
  95 /* IRQ stack memory (calculated at run-time) */
  96 .globl IRQ_STACK_START
  97 IRQ_STACK_START:
  98         .word   0x0badc0de
  99
 100 /* IRQ stack memory (calculated at run-time) */
 101 .globl FIQ_STACK_START
 102 FIQ_STACK_START:
 103         .word 0x0badc0de
 104 #endif
 105
 106
 107 /*
 108  * the actual reset code
 109  */
 110
 111 reset:
 112         /*
 113          * set the cpu to SVC32 mode
 114          */
 115         mrs     r0,cpsr
 116         bic     r0,r0,#0x1f
 117         orr     r0,r0,#0xd3
 118         msr     cpsr,r0
 119
 120 /* turn off the watchdog */
 121 #if defined(CONFIG_S3C2400)
 122 #define pWTCON          0x15300000
 123 /* Interupt-Controller base addresses */
 124 #define INTMSK          0x14400008
 125 /* clock divisor register */
 126 #define CLKDIVN         0x14800014
 127 #elif defined(CONFIG_S3C2410)
 128 #define pWTCON          0x53000000
 129 /* Interupt-Controller base addresses */
 130 #define INTMSK          0x4A000008
 131 #define INTSUBMSK       0x4A00001C
 132 /* clock divisor register */
 133 #define CLKDIVN         0x4C000014
 134 #endif
 135
 136         ldr     r0, =pWTCON
 137         mov     r1, #0x0
 138         str     r1, [r0]
 139
 140         /*
 141          * mask all IRQs by setting all bits in the INTMR - default
 142          */
 143         mov     r1, #0xffffffff
 144         ldr     r0, =INTMSK
 145         str     r1, [r0]
 146 #if defined(CONFIG_S3C2410)
 147         ldr     r1, =0x3ff
 148         ldr     r0, =INTSUBMSK
 149         str     r1, [r0]
 150 #endif
 151
 152         /* FCLK:HCLK:PCLK = 1:2:4 */
 153         /* default FCLK is 120 MHz ! */
 154         ldr     r0, =CLKDIVN
 155         mov     r1, #3
 156         str     r1, [r0]
 157
 158         /*
 159          * we do sys-critical inits only at reboot,
 160          * not when booting from ram!
 161          */
 162 #ifdef CONFIG_INIT_CRITICAL
 163         bl      cpu_init_crit
 164 #endif
 165
 166 relocate:                               /* relocate U-Boot to RAM           */
 167         adr     r0, _start              /* r0 <- current position of code   */
 168         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 169         cmp     r0, r1                  /* don't reloc during debug         */
 170         beq     stack_setup
 171
 172         ldr     r2, _armboot_start
 173         ldr     r3, _armboot_end
 174         sub     r2, r3, r2              /* r2 <- size of armboot            */
 175         add     r2, r0, r2              /* r2 <- source end address         */
 176
 177 copy_loop:
 178         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 179         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 180         cmp     r0, r2                  /* until source end addreee [r2]    */
 181         ble     copy_loop
 182
 183         /* Set up the stack                                                 */
 184 stack_setup:
 185         ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 186         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 187         sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
 188 #ifdef CONFIG_USE_IRQ
 189         sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 190 #endif
 191         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 192
 193 #if 0
 194         /* try doing this stuff after the relocation */
 195         ldr     r0, =pWTCON
 196         mov     r1, #0x0
 197         str     r1, [r0]
 198
 199         /*
 200          * mask all IRQs by setting all bits in the INTMR - default
 201          */
 202         mov     r1, #0xffffffff
 203         ldr     r0, =INTMR
 204         str     r1, [r0]
 205
 206         /* FCLK:HCLK:PCLK = 1:2:4 */
 207         /* default FCLK is 120 MHz ! */
 208         ldr     r0, =CLKDIVN
 209         mov     r1, #3
 210         str     r1, [r0]
 211         /* END stuff after relocation */
 212 #endif
 213
 214         ldr     pc, _start_armboot
 215
 216 _start_armboot: .word start_armboot
 217
 218
 219 /*
 220  *************************************************************************
 221  *
 222  * CPU_init_critical registers
 223  *
 224  * setup important registers
 225  * setup memory timing
 226  *
 227  *************************************************************************
 228  */
 229
 230
 231 cpu_init_crit:
 232         /*
 233          * flush v4 I/D caches
 234          */
 235         mov     r0, #0
 236         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 237         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 238
 239         /*
 240          * disable MMU stuff and caches
 241          */
 242         mrc     p15, 0, r0, c1, c0, 0
 243         bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 244         bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 245         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 246         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 247         mcr     p15, 0, r0, c1, c0, 0
 248
 249
 250         /*
 251          * before relocating, we have to setup RAM timing
 252          * because memory timing is board-dependend, you will
 253          * find a memsetup.S in your board directory.
 254          */
 255         mov     ip, lr
 256         bl      memsetup
 257         mov     lr, ip
 258
 259         mov     pc, lr
 260
 261
 262 /*
 263  *************************************************************************
 264  *
 265  * Interrupt handling
 266  *
 267  *************************************************************************
 268  */
 269
 270 @
 271 @ IRQ stack frame.
 272 @
 273 #define S_FRAME_SIZE    72
 274
 275 #define S_OLD_R0        68
 276 #define S_PSR           64
 277 #define S_PC            60
 278 #define S_LR            56
 279 #define S_SP            52
 280
 281 #define S_IP            48
 282 #define S_FP            44
 283 #define S_R10           40
 284 #define S_R9            36
 285 #define S_R8            32
 286 #define S_R7            28
 287 #define S_R6            24
 288 #define S_R5            20
 289 #define S_R4            16
 290 #define S_R3            12
 291 #define S_R2            8
 292 #define S_R1            4
 293 #define S_R0            0
 294
 295 #define MODE_SVC 0x13
 296 #define I_BIT    0x80
 297
 298 /*
 299  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 300  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 301  */
 302
 303         .macro  bad_save_user_regs
 304         sub     sp, sp, #S_FRAME_SIZE
 305         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 306         ldr     r2, _armboot_end
 307         add     r2, r2, #CONFIG_STACKSIZE
 308         sub     r2, r2, #8
 309         ldmia   r2, {r2 - r3}                   @ get pc, cpsr
 310         add     r0, sp, #S_FRAME_SIZE           @ restore sp_SVC
 311
 312         add     r5, sp, #S_SP
 313         mov     r1, lr
 314         stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 315         mov     r0, sp
 316         .endm
 317
 318         .macro  irq_save_user_regs
 319         sub     sp, sp, #S_FRAME_SIZE
 320         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 321         add     r8, sp, #S_PC
 322         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 323         str     lr, [r8, #0]                    @ Save calling PC
 324         mrs     r6, spsr
 325         str     r6, [r8, #4]                    @ Save CPSR
 326         str     r0, [r8, #8]                    @ Save OLD_R0
 327         mov     r0, sp
 328         .endm
 329
 330         .macro  irq_restore_user_regs
 331         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 332         mov     r0, r0
 333         ldr     lr, [sp, #S_PC]                 @ Get PC
 334         add     sp, sp, #S_FRAME_SIZE
 335         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 336         .endm
 337
 338         .macro get_bad_stack
 339         ldr     r13, _armboot_end               @ setup our mode stack
 340         add     r13, r13, #CONFIG_STACKSIZE     @ resides at top of normal stack
 341         sub     r13, r13, #8
 342
 343         str     lr, [r13]                       @ save caller lr / spsr
 344         mrs     lr, spsr
 345         str     lr, [r13, #4]
 346
 347         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 348         @ msr   spsr_c, r13
 349         msr     spsr, r13
 350         mov     lr, pc
 351         movs    pc, lr
 352         .endm
 353
 354         .macro get_irq_stack                    @ setup IRQ stack
 355         ldr     sp, IRQ_STACK_START
 356         .endm
 357
 358         .macro get_fiq_stack                    @ setup FIQ stack
 359         ldr     sp, FIQ_STACK_START
 360         .endm
 361
 362 /*
 363  * exception handlers
 364  */
 365         .align  5
 366 undefined_instruction:
 367         get_bad_stack
 368         bad_save_user_regs
 369         bl      do_undefined_instruction
 370
 371         .align  5
 372 software_interrupt:
 373         get_bad_stack
 374         bad_save_user_regs
 375         bl      do_software_interrupt
 376
 377         .align  5
 378 prefetch_abort:
 379         get_bad_stack
 380         bad_save_user_regs
 381         bl      do_prefetch_abort
 382
 383         .align  5
 384 data_abort:
 385         get_bad_stack
 386         bad_save_user_regs
 387         bl      do_data_abort
 388
 389         .align  5
 390 not_used:
 391         get_bad_stack
 392         bad_save_user_regs
 393         bl      do_not_used
 394
 395 #ifdef CONFIG_USE_IRQ
 396
 397         .align  5
 398 irq:
 399         get_irq_stack
 400         irq_save_user_regs
 401         bl      do_irq
 402         irq_restore_user_regs
 403
 404         .align  5
 405 fiq:
 406         get_fiq_stack
 407         /* someone ought to write a more effiction fiq_save_user_regs */
 408         irq_save_user_regs
 409         bl      do_fiq
 410         irq_restore_user_regs
 411
 412 #else
 413
 414         .align  5
 415 irq:
 416         get_bad_stack
 417         bad_save_user_regs
 418         bl      do_irq
 419
 420         .align  5
 421 fiq:
 422         get_bad_stack
 423         bad_save_user_regs
 424         bl      do_fiq
 425
 426 #endif
 427
 428         .align  5
 429 .globl reset_cpu
 430 reset_cpu:
 431 #ifdef CONFIG_S3C2400
 432         bl      disable_interrupts
 433 # ifdef CONFIG_TRAB
 434         bl      disable_vfd
 435 # endif
 436         ldr     r1, _rWTCON
 437         ldr     r2, _rWTCNT
 438         /* Disable watchdog */
 439         mov     r3, #0x0000
 440         str     r3, [r1]
 441         /* Initialize watchdog timer count register */
 442         mov     r3, #0x0001
 443         str     r3, [r2]
 444         /* Enable watchdog timer; assert reset at timer timeout */
 445         mov     r3, #0x0021
 446         str     r3, [r1]
 447 _loop_forever:
 448         b       _loop_forever
 449 _rWTCON:
 450         .word   0x15300000
 451 _rWTCNT:
 452         .word   0x15300008
 453 #else /* ! CONFIG_S3C2400 */
 454         mov     ip, #0
 455         mcr     p15, 0, ip, c7, c7, 0           @ invalidate cache
 456         mcr     p15, 0, ip, c8, c7, 0           @ flush TLB (v4)
 457         mrc     p15, 0, ip, c1, c0, 0           @ get ctrl register
 458         bic     ip, ip, #0x000f                 @ ............wcam
 459         bic     ip, ip, #0x2100                 @ ..v....s........
 460         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
 461         mov     pc, r0
 462 #endif /* CONFIG_S3C2400 */